公开(公告)号：EP1869557A2

公开(公告)日：2007-12-26

申请号：EP06739774.5

申请日：2006-03-23

申请人： QUALCOMM INCORPORATED

发明人： SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

摘要翻译： 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中的任何复制条目是否包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含修改的数据，则从内存中读取的数据将被写入所选条目，而无需先阅读条目。 在银行缓存中，两个或更多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否提高了处理器性能并降低了功耗。

公开(公告)号：EP1869547A2

公开(公告)日：2007-12-26

申请号：EP06750153.6

申请日：2006-04-14

申请人： Qualcomm Incorporated

发明人： SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

IPC分类号： G06F9/38

CPC分类号： G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

摘要： A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so that it unconditionally provides an output to the target. The conditional instruction obtains the prior value of the target (that is, the value produced by the most recent instruction preceding the conditional instruction that updated that target). The condition is evaluated. If the condition is satisfied, an operation is performed and the result of the operation output to the target. If the condition is not satisfied, the prior value is output to the target. Subsequent instructions may rely on the target as an operand source (whether written to a register or forwarded to the instruction), prior to the condition evaluation.

公开(公告)号：EP1853998A1

公开(公告)日：2007-11-14

申请号：EP06737321.7

申请日：2006-03-06

申请人： QUALCOMM INCORPORATED

发明人： DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  MCILVAINE, Michael, Scott ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/3001 ,  G06F9/30072

摘要： The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition is made. If the condition is such that the instruction will not execute on this pass through the pipeline, the hold with regard to the conditional instruction may be terminated, that is to say skipped or stopped prior to completion of receiving all the associated operand data. Flow of the non-executing instruction through the pipeline, for example, need not wait for an earlier instruction to compute and write source operand data for use by the conditional instruction.

公开(公告)号：EP2972898B1

公开(公告)日：2017-11-22

申请号：EP14729747.7

申请日：2014-03-11

申请人： Qualcomm Incorporated

发明人： KOOB, Christopher, Edward ,  PLONDKE, Erich, James ,  PATEL, Piyush ,  SARTORIUS, Thomas, Andrew ,  CODRESCU, Lucian

IPC分类号： G06F12/10

CPC分类号： G06F12/10 ,  G06F12/1009 ,  G06F12/109 ,  G06F2212/1008 ,  G06F2212/1048 ,  G06F2212/1052 ,  G06F2212/657

公开(公告)号：EP1869557B1

公开(公告)日：2017-09-27

申请号：EP06739774.5

申请日：2006-03-23

申请人： QUALCOMM INCORPORATED

发明人： SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris

IPC分类号： G06F12/08 ,  G06F12/0804

CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

摘要翻译： 处理器包括具有根据回拷算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示缓存中的任何回拷条目是否包含修改后的数据。 在高速缓存未命中时，如果GMI指示高速缓存中没有任何回拷条目包含修改后的数据，则从内存中取回的数据将被写入所选条目，而无需先读取条目。 在银行缓存中，两个或更多银行GMI可能与两个或更多银行相关联。 在n路组关联高速缓存中，n个集合GMI可以与n个集合相关联。 抑制读取以确定回拷缓存条目是否包含修改的数据可提高处理器性能并降低功耗。

公开(公告)号：EP1941375B1

公开(公告)日：2017-08-30

申请号：EP06846130.0

申请日：2006-10-20

申请人： QUALCOMM Incorporated

发明人： BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  SMITH, Rodney, Wayne

IPC分类号： G06F12/10 ,  G06F12/1045 ,  G06F12/14

CPC分类号： G06F12/1063 ,  G06F12/1054 ,  G06F12/145 ,  Y02D10/13

摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.

摘要翻译： 处理系统可以包括被配置为将数据存储在多个页面中的存储器，TLB以及包括多个高速缓存行的存储器高速缓存。 存储器中的每个页面可以包括多行存储器。 当虚拟地址被呈现给高速缓存时，存储器高速缓存可以允许从多个高速缓存行中标识的匹配高速缓存行，匹配高速缓存行具有匹配虚拟地址的匹配地址。 存储器高速缓存可被配置为通过进一步在每个高速缓存行中存储行的页面属性，允许从存储器高速缓存而不是从TLB中检索位于匹配地址处的页面的一个或多个页面属性 存储在缓存行中的数据。

公开(公告)号：EP1869547B1

公开(公告)日：2016-09-21

申请号：EP06750153.6

申请日：2006-04-14

申请人： Qualcomm Incorporated

发明人： SARTORIUS, Thomas, Andrew ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  DOCKSER, Kenneth, Alan c/o QUALCOMM Incorporated ,  MCILVAINE, Michael, Scott ,  SMITH, Rodney, Wayne

IPC分类号： G06F9/38

CPC分类号： G06F9/30072 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/384

公开(公告)号：EP2994837A1

公开(公告)日：2016-03-16

申请号：EP14728008.5

申请日：2014-04-22

申请人： Qualcomm Incorporated

发明人： SHARP, Colin, Christopher ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/1009 ,  G06F12/145

摘要： A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.

公开(公告)号：EP2569695A1

公开(公告)日：2013-03-20

申请号：EP11722646.4

申请日：2011-04-27

申请人： Qualcomm Incorporated

发明人： SARTORIUS, Thomas, Andrew

IPC分类号： G06F9/34 ,  G06F9/35 ,  G06F9/445 ,  G06F12/10 ,  G06F13/28

CPC分类号： G06F9/34 ,  G06F9/35 ,  G06F12/1027 ,  G06F12/1081 ,  Y02D10/13

摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.

摘要翻译： 配置替代存储器用于转换并存储数据值说明使用指令的访问代理。 在一个，该指令被接收到的实施方式做了包括第一操作数指定将被翻译的数据值和第二操作数指定与替代存储器存取代理寄存器在其中存储的数据值的位置相关联的虚拟地址。 的数据值可以被转换为第一物理地址。 虚拟地址可以被翻译成第二物理地址。 所述第一物理地址被存储在所述替代存储器基于所述第二物理地址访问代理注册。

公开(公告)号：EP2126689B8

公开(公告)日：2010-12-29

申请号：EP08713989.5

申请日：2008-01-24

申请人： QUALCOMM Incorporated

发明人： MCILVAINE, Michael, Scott ,  DIEFFENDERFER, James, Norris ,  NUNAMAKER, Nathan, Samuel ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3017 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： Intermediate results are passed between constituent instructions of an expanded instruction using register renaming resources and control logic. A first constituent instruction generates intermediate results and is assigned a PRN in a constituent instruction rename table, and writes intermediate results to the identified physical register. A second constituent instruction performs a look up in the constituent instruction rename table and reads the intermediate results from the physical register. Constituent instruction rename logic tracks the constituent instructions through the pipeline, and delete the constituent instruction rename table entry and returns the PRN to a free list when the second constituent instruction has read the intermediate results.