-
公开(公告)号：EP1073115A2
公开(公告)日：2001-01-31
申请号：EP00306332.8
申请日：2000-07-25
发明人： Gruening, Ulrike , Radens, Carl J. , Tobben, Dirk
IPC分类号： H01L21/8242
CPC分类号： H01L27/1087
摘要： A process for manufacturing a deep trench capacitor in a trench. The capacitor comprises a collar in an upper region of the trench and a buried plate in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.
摘要翻译： 一种在沟槽（10）中制造深沟槽电容器的工艺。 电容器包括在沟槽的上部区域中的环（18）和在沟槽的下部区域中的掩埋板（26）。 改进之处在于，在沟槽上部区域中形成套环之前，用诸如旋涂玻璃的非感光底部填充材料（16）填充沟槽下部区域。 该方法可以包括以下步骤：（a）在衬底中形成深沟槽; （b）用底部填充材料填充沟槽下部区域; （c）在所述沟槽上部区域中形成套环; （d）去除底层填料; 和（e）在沟槽下部区域形成掩埋板。
-
公开(公告)号：EP0940853A3
公开(公告)日：2003-08-06
申请号：EP99102356.5
申请日：1999-02-06
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
-
23.发明公开DRAM trench capacitor cell and method of fabricating the same 审中-公开DRAM-Grabenkondensator-Zelle und Verfahren zur Herstellung derselben
公开(公告)号：EP0940853A2
公开(公告)日：1999-09-08
申请号：EP99102356.5
申请日：1999-02-06
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.
摘要翻译： 通过首先形成由晶片的主体部分隔开的一对垂直沟槽，在硅晶片的单晶体部分中形成用于DRAM中的一对存储单元。 在每个沟槽的壁上形成电介质层之后，各沟槽都被多晶硅填充。 通过一对凹陷形成和凹陷填充步骤，在每个沟槽的顶部形成有与中间体部分外延生长的硅区域。 使每个外延区域用作在沟槽的下多晶硅填充物中具有其漏极的单独晶体管的主体，并且其源在两个外延区域之间的单晶体体中间。 每个沟槽的较低多晶硅填充物也用作每个电池的电容器的存储节点，其中该体积用作电容器的另一个板。
-
公开(公告)号：EP0996151A3
公开(公告)日：2000-06-07
申请号：EP99117761.9
申请日：1999-09-09
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译： 提供一种用于在半导体本体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。 第一栅极氧化物层和第一多晶硅层沉积在有源区上方的半导体本体上。 在所述第一栅极氧化物和多晶硅层以及所述半导体主体中刻蚀沟槽以划定第一和第二有源区域，从而形成第一轮廓栅极氧化物层和与第一有源区域共同延伸的多晶硅层。 材料沉积在所述沟槽中以形成有源区隔离，有源区隔离具有在所述半导体主体上方的顶表面。 然后在所述第一和第二有源区域上方形成掩模层，并去除它的选择部分以暴露所述第二有源区域。 掩模层和有源区隔离一起形成掩模，该掩模限定与第二有源区共同扩展的开口，其中有源区隔离限定了所述开口。 材料穿过开口以形成第二栅极氧化物层和第二多晶层，该第二层和第二多晶层与第二有源区共延。 具有第一描绘栅极氧化物和多晶层的第一晶体管作为第一晶体管和第二晶体管的多个层的对，第二栅极氧化物层和第二多晶层作为一对多层 的第二晶体管。
-
公开(公告)号：EP0996151A2
公开(公告)日：2000-04-26
申请号：EP99117761.9
申请日：1999-09-09
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译： 提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。 第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。 在所述第一栅极氧化物和多晶硅层以及所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。 材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。 然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。 屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。 通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。 第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管和第二晶体管的多个层的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层 的第二晶体管。
-
-
-
-
搜索结果
25 条记录 (耗时 0.011 秒)
