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公开(公告)号：EP0377327B1
公开(公告)日：1994-01-05
申请号：EP89313651.5
申请日：1989-12-28
发明人： Fox, David Alan
IPC分类号： H02P9/10
CPC分类号： H02P9/102 , H02P2101/30
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公开(公告)号：EP0376725A3
公开(公告)日：1991-11-21
申请号：EP89313650.7
申请日：1989-12-28
IPC分类号： H02P9/30
CPC分类号： H02P9/30 , H02P2101/30
摘要： An electric generating system having a discharge circuit for a DC filter capacitor includes an electric power source 10, 18 for producing a DC voltage on a pair of conductors 20, 22 and a DC filter capacitor 24 electrically connected between the conductors. A voltage indicating signal, representative of the actual output voltage of the generator, is combined with a reference signal to obtain a control signal which varies in proportion to the difference between the desired output voltage of the power source and the actual output voltage. Power source output voltage is controlled in response to the control signal. A branch circuit 46 with a solid state switching device is connected across the DC filter capacitor. The solid state switching device is turned on for a limited time in response to a change in the magnitude of the control signal resulting from an increase in the actual output voltage of the power source, thereby discharging the DC filter capacitor.
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23.发明公开Method and circuit for controlling the frequency of an electronic inverter 失效Verfahren und Schaltung zur Steuerung der Frequenz eines elektronischen Wechselrichter。
公开(公告)号：EP0446527A2
公开(公告)日：1991-09-18
申请号：EP90313709.9
申请日：1990-12-14
CPC分类号： H03B23/00 , H03B2200/0092 , H03K5/156 , H03K23/662
摘要： A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which, the frequency of the control signal is incremented.
摘要翻译： 一种用于修改时钟信号的频率的方法包括以下步骤：产生具有以第一频率发生的电压脉冲的时钟信号，并产生具有以较低频率发生的电压脉冲的控制信号。 控制信号中的电压脉冲的频率以连续的时间间隔递增，并且组合时钟信号和控制信号，使得控制信号中的每个电压脉冲中的时钟信号中的一个电压脉冲被删除。 这导致修改的时钟信号具有根据控制信号的初始频率和控制信号的频率增加的方向可以上升或下降的频率。
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公开(公告)号：EP0350300A3
公开(公告)日：1990-12-19
申请号：EP89306853.6
申请日：1989-07-06
CPC分类号： H03K17/668 , H03K17/04213
摘要： A solid state power controller is provided with an output circuit having a transistor (Q1) which is connected between a pair of output terminals (10, 12). Base current to the transistor is provided by a drive circuit (14) which includes a pair of series connected diodes (D1, D2) that provide biasing to offset the drive circuit and output transistor base voltage drops. Load current is sensed and a DC bias current is supplied to the diode pair, with the DC bias current being proportional to the load current. For bi-directional operation, a second output transistor is connected in series with the first output transistor and a pair of reverse series connected diodes (D7, D8) are connected in a circuit branch which parallels the two output transistors. Junction points between the output transistors and the reverse series connected diode circuit branch are connected together to provide for bidirectional load current flow.
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25.发明公开
公开(公告)号：EP0301905A3
公开(公告)日：1990-07-18
申请号：EP88307055.9
申请日：1988-07-29
发明人： Fox, David Alan
IPC分类号： H02J3/42
CPC分类号： H02M7/48 , H02J3/42 , Y10T307/576 , Y10T307/615 , Y10T307/625 , Y10T307/735
摘要： Power sources (10, 24) of a parallel AC electrical power system are synchronized by producing a voltage difference signal representative of the difference in output voltages of the power sources and demodulating that signal to produce a frequency control signal and a voltage magnitude control signal. The output frequency and voltage magnitude of at least one of the power sources is varied in response to the frequency control signal and voltage magnitude control signals, respectively, to minimize the difference in output voltages between the power sources.
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公开(公告)号：EP0473428A2
公开(公告)日：1992-03-04
申请号：EP91307910.9
申请日：1991-08-29
发明人： Beg, Mirza Akmal , Fox, David Alan
摘要： An overcurrent trip circuit monitors the rate of rise of the current and the magnitude of the current in a power conductor 14 and opens a circuit containing the power conductor when either the rate of rise of the current exceeds a first preselected limit value or the magnitude of the current exceeds a second preselected limit value. The inherent inductance in a metering shunt 18 is used to produce a voltage signal that contains a component which is representative of the rate of change of current in a power conductor. This voltage signal is compared to a first reference signal to produce a trip signal when the voltage exceeds the first reference signal. In addition, the voltage signal is processed and the processed voltage signal is compared to a second reference signal to produce a second trip signal when the magnitude of the processed voltage signal exceeds the magnitude of the second reference signal. The power circuit is then opened in response to either of the first or second trip signals.
摘要翻译： 过电流跳闸电路监测电流的上升速率和电力导体14中的电流的大小，并且当电流的上升速率超过第一预选极限值或者当电流的上升幅度超过 电流超过第二预选极限值。 计量分流器18中的固有电感用于产生包含表示电力导体中的电流变化率的分量的电压信号。 该电压信号与第一参考信号进行比较，以在电压超过第一参考信号时产生跳闸信号。 此外，当处理的电压信号的大小超过第二参考信号的幅度时，处理电压信号并将处理的电压信号与第二参考信号进行比较以产生第二跳闸信号。 然后响应于第一或第二跳闸信号中的任何一个而断开电源电路。
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27.发明公开
公开(公告)号：EP0467675A2
公开(公告)日：1992-01-22
申请号：EP91306526.4
申请日：1991-07-18
发明人： Fox, David Alan
摘要： An inverse time delay circuit includes an integrator 10 for receiving a signal representative of a voltage or current in an external circuit and a reference signal. The integrator produces a control signal representative of the integral of the difference between the signals. A comparator U2 compares the control signal to a second reference signal to produce an output which changes logic states when the magnitude of the control signals exceeds the magnitude of the second reference signal. A circuit is provided to control the magnitudes of one or both of the reference signals thereby providing control of the instantaneous and/or ultimate trip levels of the circuit.
摘要翻译： 逆时间延迟电路包括用于接收表示外部电路中的电压或电流的信号的积分器10和参考信号。 积分器产生表示信号之间的差的积分的控制信号。 比较器U2将控制信号与第二参考信号进行比较，以产生当控制信号的幅度超过第二参考信号的幅度时改变逻辑状态的输出。 提供电路以控制一个或两个参考信号的幅度，从而提供对电路的瞬时和/或最终跳闸电平的控制。
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28.发明公开
公开(公告)号：EP0446527A3
公开(公告)日：1991-10-23
申请号：EP90313709.9
申请日：1990-12-14
CPC分类号： H03B23/00 , H03B2200/0092 , H03K5/156 , H03K23/662
摘要： A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which, the frequency of the control signal is incremented.
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公开(公告)号：EP0350299A3
公开(公告)日：1990-12-19
申请号：EP89306852.8
申请日：1989-07-06
CPC分类号： H02H3/087 , H02J1/10 , H03K17/68 , H03K2217/0009 , H03K2217/0027
摘要： A bi-directional DC power controller is provided with a bi-directional DC switch (10) connected between a pair of terminals (12, 14) for connection to a pair of line power conductors (16, 20). A pair of difference amplifiers (U2, U3) are connected to receive voltages at these terminals. Each amplifier produces an output voltage signal which is proportional to the difference in voltages between these terminals when the voltage at one of the terminals is greater than the voltage at the other terminal, and is constant when the voltage at the second terminal is greater than the voltage at the first terminal. The outputs of the difference amplifiers are combined to produce a control voltage signal having a magnitude that is proportional to the absolute value of the difference between voltages at the terminals. This control signal is used to control the operation of the bi-directional DC switch.
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公开(公告)号：EP0376726A3
公开(公告)日：1990-08-29
申请号：EP89313653.1
申请日：1989-12-28
发明人： Fox, David Alan
IPC分类号： H02P9/10
CPC分类号： H02P9/305 , H02P9/102 , H02P2101/30
摘要： A generator voltage regulator circuit is provided with a switching circuit for alternatively connecting or disconnecting a generator exciter field winding 12 to a DC power source 10. A discharge circuit CR1, CR2 is provided for conducting current, produced by a collapsing magnetic field in the exciter winding following disconnection of the winding by the switching circuit 14, in a reverse direction through the DC power source. A driving circuit 26 controls the switching circuit with a series of turn-on pulses. Each of the turn-on pulses is initiated in response to a transition in a clock signal and is terminated alternatively when the current in the exciter field winding reaches a predetermined magnitude or when a second transition occurs in the clock signal. This invention also encompasses a method of regulating exciter field current performed by this circuit.
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