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52 条记录 (耗时 0.012 秒)

    Driving circuit for a bipolar transistor in common-base mode having a resonant load
    3.
    发明公开
    Driving circuit for a bipolar transistor in common-base mode having a resonant load 有权
    驱动电路的双极晶体管的控制端子接通电源和谐振负载

    公开(公告)号：EP1455453A1

    公开(公告)日：2004-09-08

    申请号：EP03425141.3

    申请日：2003-03-05

    申请人： STMicroelectronics S.r.l.

    发明人： Scollo, Rosario ,  Buonomo, Simone

    IPC分类号： H03K17/567 ,  H03K17/64

    CPC分类号： H03K17/567 ,  H03K17/04213

    摘要： The invention relates to a driving circuit for a control terminal (B1) of a bipolar transistor (T1) inserted, in the emitter-switching configuration, between a resonant load (3) and a voltage reference (GND), the driving circuit comprising at least a capacitor (C2) connected between the control terminal (B1) and the voltage reference (GND).
    Advantageously according to the invention, the driving circuit further comprises:

    an additional resonance capacitor (C1b) connected between a collector terminal (TC1) of the bipolar transistor (T1) and a circuit node (X3);
    a first diode (D2) inserted between the circuit node (X3) and the control terminal (B1); and
    a second diode (D3) inserted between the circuit node (X3) and the voltage reference (GND).

    The invention also relates to a driving method for a control terminal (B1) of a bipolar transistor (T1) in the emitter-switching configuration.

    摘要翻译： 本发明涉及一种用于插入一个双极型晶体管（T1）的控制端子（B1）的驱动电路，在发射极开关的配置，（3）和参考电压（GND），所述驱动电路，包括在谐振负载之间 至少连接在控制端子（B1）和电压基准（GND）之间的电容器（C2）。 有利地gemäß所述的发明，所述驱动电路还包括：连接在集电极端子双极晶体管的（TC1）（T1）和一个电路节点（X3）之间的附加谐振电容器（C1B）; 电路节点（X3）和控制端子（B1）之间插入的第一二极管（D2）; 和第二二极管（D3）的电路节点（X3）和参考电压（GND）之间插入。 因此，本发明涉及一种用于在发射极开关结构的双极型晶体管（T1）的控制端子（B1）的驱动方法。

    Reduction of the transition delay of an output power transistor
    5.
    发明公开
    Reduction of the transition delay of an output power transistor 失效
    Verringerung derÜbergangszeiteines Ausgangsleistungstransistors。

    公开(公告)号：EP0627818A1

    公开(公告)日：1994-12-07

    申请号：EP93830246.0

    申请日：1993-05-31

    申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

    发明人： Nessi, Maurizio

    IPC分类号： H03K17/16 ,  H03K17/04

    CPC分类号： H03K17/04213 ,  H03K17/166

    摘要： A fast-discharge switch (M1) is controlled by a comparator (M2) sensing the voltage difference between the output node and the input node of a driving integrator stage that controls the slew-rate of a power switching output transistor (MP). The fast-discharge switch turns off automatically when the output power transistor reaches (in the case of a MOS transistor) or exits (in the case of a bipolar transistor) saturation. The circuit of the invention accelerates the discharge thus reducing the turn-off delay and is insensitive of load conditions and does not affect the performance of the integrating (driver) stage that control the slew-rate.

    摘要翻译： 快速放电开关（M1）由感测输出节点和控制功率开关输出晶体管（MP）的转换速率的驱动积分器级的输入节点之间的电压差的比较器（M2）控制。 当输出功率晶体管达到（在MOS晶体管的情况下）或退出（在双极晶体管的情况下）饱和时，快速放电开关自动关闭。 本发明的电路加速了放电，从而降低了关断延迟，并且对负载条件不敏感，并且不影响控制转换速率的积分（驱动器）级的性能。

    CIRCUIT ARRANGEMENT FOR GENERATING HIGH VOLTAGE PULSES
    6.
    发明授权
    CIRCUIT ARRANGEMENT FOR GENERATING HIGH VOLTAGE PULSES 失效
    用于产生高电压脉冲的电路装置

    公开(公告)号：EP0219504B1

    公开(公告)日：1990-08-29

    申请号：EP85904479.4

    申请日：1985-09-06

    申请人： KOVACS, Adam

    发明人： KOVACS, Adam

    IPC分类号： H02M3/24 ,  H05B41/26

    CPC分类号： H03K17/64 ,  H02M3/3385 ,  H03K17/04213 ,  H03K17/08146

    摘要： A circuit arrangement for generating high voltage pulses from DC voltage comprising a transformer, a secondary winding and at least two primary windings of said transformer, said primary windings at least one diode and a switching circuit are serial connected; said series circuit is connected to a voltage source, a capacitor is connected to the common terminal of said voltage source and of said primary windings, further said switching circuit is formed from the emitter-collector-section of a switching transistor, on the base of said switching transistor the output of a transistor amplifier is connected and the input of said transistor amplifier is coupled with the output of the control circuit. According to the invention the input (18) of said transistor amplifier (15) is formed from the base of a second transistor (30), between said input (18) and the output of said control circuit (16) two serial connected resistors (17a and 17b) are inserted, to the common terminal of both said resistors (17a and 17b) the emitter-collector-section of a first transistor (24) is connected, to the base of said first transistor (24) a voltage divider is connected, the branch (25) of which standing on the collector side is divided and connected to said voltage source (7), between the dividing point of said branch (25) and the common terminal of said primary winding (3) of said transformer (1) and of said switching transistor (14) a capacitor (26) is inserted, the resistor (27) of said voltage divider inserted on the emitter side is connected to a current control resistor (28), which is in series with the emitter-collector-circuit of said switching transistor (14).

    Alimentation électrique
    7.
    发明公开
    Alimentation électrique 失效
    电源。

    公开(公告)号：EP0208588A1

    公开(公告)日：1987-01-14

    申请号：EP86401353.7

    申请日：1986-06-20

    申请人： THOMSON-CSF

    发明人： Frappe, Gérard ,  Ortalli, Patrice

    IPC分类号： H03K17/60 ,  H03K17/04

    CPC分类号： H03K17/04213 ,  H03K17/60

    摘要： L'invention a principalement pour objet une alimentation élec­trique. Le dispositif objet de la présente invention, permet une commutation rapide des diodes PIN (2) de leur état passant à leur état bloqué tout en limitant les puissances électriques nécessaires. Pour cela on utilise une boucle d'amplification de courant per­mettant sur commande d'amener quasi instantanément le courant à la valeur désirée, tout en maintenant une consommation faible au repos. Il est particulièrement avantageux d'associer ce système à un générateur de basse tension (60) permettant l'élimination de porteurs minoritaires. En effet dans ce cas le générateur de haute tension (1) permettant le blocage de la diode a des temps de repos plus importants. Avantageusement l'invention est réalisée sous forme d'un circuit intégré.
    L'invention s'applique principalement à la réalisation des déphaseurs pour antennes à balayage électronique et à diodes PIN auxdites antennes ainsi qu'aux radars comportant lesdites antennes.

    Output stage for a digital circuit
    8.
    发明公开
    Output stage for a digital circuit 失效
    数字电路的输出级

    公开(公告)号：EP0496277A3

    公开(公告)日：1993-07-28

    申请号：EP92100658.1

    申请日：1992-01-16

    申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

    发明人： Jungert, Horst

    IPC分类号： H03K17/04

    CPC分类号： H03K17/04213 ,  H03K17/666

    摘要： An output stage for a digital circuit for emitting a signal with the one or the other binary value in dependence upon an input signal includes an output transistor (T1) at the collector of which the signal to be emitted can be tapped off and to the base of which a current dependent on the input signal is supplied. In the line leading to the base of the output transistor (T1) a device (R1, 24) is disposed for setting the base current in dependence upon the current flowing through the collector-emitter path of the output transistor (T1).

    Output stage for a digital circuit
    9.
    发明公开
    Output stage for a digital circuit 失效
    Ausgangstufefüreine digitale Schaltung。

    公开(公告)号：EP0496277A2

    公开(公告)日：1992-07-29

    申请号：EP92100658.1

    申请日：1992-01-16

    申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

    发明人： Jungert, Horst

    IPC分类号： H03K17/04

    CPC分类号： H03K17/04213 ,  H03K17/666

    摘要： An output stage for a digital circuit for emitting a signal with the one or the other binary value in dependence upon an input signal includes an output transistor (T1) at the collector of which the signal to be emitted can be tapped off and to the base of which a current dependent on the input signal is supplied. In the line leading to the base of the output transistor (T1) a device (R1, 24) is disposed for setting the base current in dependence upon the current flowing through the collector-emitter path of the output transistor (T1).

    摘要翻译： 用于根据输入信号发射具有一个或另一个二进制值的信号的数字电路的输出级包括在集电极处的输出晶体管（T1），其中待发射的信号可以被分接出并且到基极 其中提供取决于输入信号的电流。 在通向输出晶体管（T1）的基极的一行中，设置器件（R1,24），用于根据流过输出晶体管（T1）的集电极 - 发射极路径的电流来设置基极电流。