公开(公告)号：EP3794594A1

公开(公告)日：2021-03-24

申请号：EP19804142.8

申请日：2019-04-16

申请人： Silicon Storage Technology, Inc.

发明人： LIANG, Hsuan ,  YANG, Jeng-Wei ,  WU, Man-Tang ,  DO, Nhan ,  TRAN, Hieu, Van

IPC分类号： G11C16/16 ,  G11C16/04

公开(公告)号：EP3320561B1

公开(公告)日：2020-08-26

申请号：EP16741416.8

申请日：2016-06-17

申请人： Silicon Storage Technology, Inc.

发明人： YANG, Jeng-Wei ,  WU, Man-Tang ,  CHEN, Chun-Ming ,  TADAYONI, Mandana ,  SU, Chien-Sheng ,  DO, Nhan

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

公开(公告)号：EP3266039B1

公开(公告)日：2019-10-16

申请号：EP16711425.5

申请日：2016-03-02

申请人： Silicon Storage Technology Inc.

发明人： CHEN, Chung-Ming ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  WU, Man-Tang ,  DO, Nhan

IPC分类号： H01L21/28 ,  G11C16/04 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11534

公开(公告)号：EP3371812A1

公开(公告)日：2018-09-12

申请号：EP16862683.6

申请日：2016-10-14

申请人： Silicon Storage Technology Inc.

发明人： ZHOU, Feng ,  LIU, Xian ,  YANG, Jeng-Wei ,  DO, Nhan

IPC分类号： G11C16/04 ,  H01L21/336 ,  H01L21/8239 ,  H01L29/778 ,  H01L29/788

CPC分类号： H01L29/7883 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66825

摘要： A non-volatile memory cell that includes a silicon substrate, source and drain regions formed in the silicon substrate (where a channel region of the substrate is defined between the source and drain regions), a metal floating gate disposed over and insulated from a first portion of the channel region, a metal control gate disposed over and insulated from the metal floating gate, a polysilicon erase gate disposed over and insulated from the source region, and a polysilicon word line gate disposed over and insulated from a second portion of the channel region.

公开(公告)号：EP3357092A1

公开(公告)日：2018-08-08

申请号：EP16753518.6

申请日：2016-08-02

申请人： Silicon Storage Technology Inc.

发明人： ZHOU, Feng ,  LIU, Xian ,  YANG, Jeng-Wei ,  SU, Chien-Sheng ,  DO, Nhan

IPC分类号： H01L29/423 ,  H01L29/788 ,  H01L29/66

摘要： A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates.

公开(公告)号：EP3243219A1

公开(公告)日：2017-11-15

申请号：EP15798284.4

申请日：2015-11-06

申请人： Silicon Storage Technology Inc.

发明人： CHEN, Chun-Ming ,  WU, Man-Tang ,  YANG, Jeng-Wei ,  SU, Chien-Sheng

IPC分类号： H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  G11C16/04

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/7885

摘要： A non-volatile memory cell including a substrate having first and second regions with a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over and insulated from a second portion of the channel region which is adjacent to the second region. The select gate includes a block of polysilicon material and a work function metal material layer extending along bottom and side surfaces of the polysilicon material block. The select gate is insulated from the second portion of the channel region by a silicon dioxide layer and a high K insulating material layer. A control gate is disposed over and insulated from the floating gate, and an erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.