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    Single-poly floating-gate memory device
    3.
    发明公开
    Single-poly floating-gate memory device 审中-公开
    单多晶浮栅存储器件

    公开(公告)号：EP2637200A1

    公开(公告)日：2013-09-11

    申请号：EP12193200.8

    申请日：2012-11-19

    申请人： eMemory Technology Inc.

    发明人： Hsu, Te-Hsun ,  Chen, Hsin-Ming ,  Yang, Ching-Sung ,  Ching, Wen-Hao ,  Chen, Wei-Ren

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04

    CPC分类号： H01L21/28273 ,  G11C16/0441 ,  G11C2216/10 ,  H01L27/11529 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7885

    摘要： An erasable programmable single-poly nonvolatile memory cell includes a floating-gate transistor having a floating gate (36), a gate oxide layer (362) under the floating gate, and a channel region; and an erase gate region (35), wherein the floating gate (36) is extended to and is adjacent to the erase gate region (35). The gate oxide layer (362) comprises a first portion (362a) above the channel region of the floating gate transistor and a second portion (362b)above the erase gate region (35), and a thickness of the first portion (362a) of the gate oxide layer is different from a thickness of the second portion (362b)of the gate oxide layer. The memory cell also comprises a select transistor in series with the floating-gate transistor.

    摘要翻译： 一种可擦除可编程单层非易失性存储单元包括具有浮置栅极（36），浮置栅极下的栅极氧化物层（362）和沟道区域的浮置栅极晶体管; 和擦除栅极区域（35），其中所述浮动栅极（36）延伸到并且与所述擦除栅极区域（35）相邻。 栅极氧化物层（362）包括在浮置栅极晶体管的沟道区上方的第一部分（362a）和在擦除栅极区（35）上方的第二部分（362b），并且第一部分（362a）的厚度 栅极氧化物层不同于栅极氧化物层的第二部分（362b）的厚度。 存储器单元还包括与浮栅晶体管串联的选择晶体管。

    DOUBLE GATE TRANSISTOR AND METHOD OF MANUFACTURING SAME
    5.
    发明公开
    DOUBLE GATE TRANSISTOR AND METHOD OF MANUFACTURING SAME 审中-公开
    双栅极晶体管及其制造方法

    公开(公告)号：EP2044619A2

    公开(公告)日：2009-04-08

    申请号：EP07766657.6

    申请日：2007-06-06

    申请人： NXP B.V.

    发明人： SONSKY, Jan ,  VAN DUUREN, Michiel, J.

    IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423

    CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7885

    摘要： A double gate transistor on a semiconductor substrate (2) includes a first diffusion region (S2), a second diffusion region (S3), and a double gate (FG, CG). The first and second diffusion regions (S2, S3) are arranged in the substrate spaced by a channel region (CR). The double gate includes a first gate electrode (FG) and a second gate electrode (CG). The first gate electrode is separated from the second gate electrode by an interpoly dielectric layer (IPD). The first gate electrode is arranged above the channel region and is separated from the channel region by a gate oxide layer (G). The second gate electrode is shaped as a central body. The interpoly dielectric layer is arranged as a conduit-shaped layer surrounding an external surface (A1) of the body of the second gate electrode. The interpoly dielectric layer is surrounded by the first gate electrode.

    Nonvolatile semiconductor memory device
    8.
    发明公开
    Nonvolatile semiconductor memory device 审中-公开
    非易失性半导体存储器件

    公开(公告)号：EP1837917A1

    公开(公告)日：2007-09-26

    申请号：EP07005513.2

    申请日：2007-03-16

    申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    发明人： Yamazaki, Shunpei ,  Asami, Yoshinobu ,  Takano, Tamae ,  Furuno, Makoto

    IPC分类号： H01L29/788 ,  H01L29/423

    CPC分类号： H01L29/42324 ,  H01L29/513 ,  H01L29/7883 ,  H01L29/7885

    摘要： A nonvolatile semiconductor memory device which is superior in writing property and charge holding property, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over the semiconductor substrate. The floating gate includes at least two layers. It is preferable that a band gap of a first layer included in the floating gate, which is in contact with the first insulating layer, be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material for forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by lowering the bottom energy level of a conduction band of the floating gate electrode than that of the channel formation region in the semiconductor substrate, a carrier injecting property and a charge holding property are improved.

    摘要翻译： 一种非易失性半导体存储装置，其特征在于，包括：在一对杂质区域之间形成有沟道形成区域的半导体基板;以及第一绝缘层，浮置栅极，第二绝缘层， 以及在半导体衬底上的控制栅极。 浮栅包括至少两层。 优选的是，与第一绝缘层接触的浮置栅极中包括的第一层的带隙小于半导体衬底的带隙。 例如，用于形成浮栅的半导体材料的带隙优选比半导体衬底中的沟道形成区域的带隙小0.1eV以上。 这是因为，通过降低浮置栅电极的导带底能级比半导体衬底中的沟道形成区的导带底能级高，载流子注入性能和电荷保持性能得到改善。

    VERFAHREN ZUR HERSTELLUNG EINER SPEICHERZELLE MIT MOS-TRANSISTOR
    9.
    发明授权
    VERFAHREN ZUR HERSTELLUNG EINER SPEICHERZELLE MIT MOS-TRANSISTOR 有权
    方法用于制造具有MOS晶体管的存储单元

    公开(公告)号：EP1060519B1

    公开(公告)日：2007-04-25

    申请号：EP98966780.3

    申请日：1998-12-17

    申请人： Qimonda AG

    发明人： HOFMANN, Franz ,  WILLER, Josef

    IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/7885

    摘要： The present invention relates to a memory cell including a vertical MOS transistor which comprises a first electrically-isolated gate electrode as well as a second gate electrode. The second gate electrode (140) is partially located in a trench while the MOS transistor is adjacent to the flange of said trench. The first gate electrode is located outside the trench and has a tip (90, 100) at the edge of said trench intended for programmation using a reduced current flow. This memory cell can be manufactured according to an automatic adjustment method so as to obtain overall dimensions of 6 F2.