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1.发明公开
公开(公告)号：EP3371829A1
公开(公告)日：2018-09-12
申请号：EP16862684.4
申请日：2016-10-17
发明人： SU, Chien-sheng , ZHOU, Feng , YANG, Jeng-Wei , TRAN, Hieu, Van , DO, Nhan
IPC分类号： H01L27/115 , B82Y10/00 , G06F13/00 , G11C16/04 , G11C16/10
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/788 , H01L29/7881
摘要： A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.
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公开(公告)号：EP3365894A1
公开(公告)日：2018-08-29
申请号：EP16858026.4
申请日：2016-10-14
发明人： CHEN, Chun-Ming , WU, Man-Tang , YANG, Jeng-Wei , SU, Chien-Sheng , DO, Nhan
CPC分类号： H01L27/11521 , G11C16/0408 , H01L21/28273 , H01L29/42328 , H01L29/66825 , H01L29/788
摘要： A method of forming a non-volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.
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3.发明公开SPLIT GATE NON-VOLATILE MEMORY CELL WITH 3D FINFET STRUCTURE, AND METHOD OF MAKING SAME 审中-公开具有3D FINFET结构的分裂栅非易失性存储器单元及其制造方法
公开(公告)号：EP3271936A1
公开(公告)日：2018-01-24
申请号：EP16708579.4
申请日：2016-02-26
发明人： SU, Chien-Sheng , YANG, Jeng-Wei , WU, Man-Tang , TRAN, Hieu Van , DO, Nhan , CHEN, Chun-Ming
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/788 , H01L27/115
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/1052 , H01L27/11551 , H01L29/0847 , H01L29/42328 , H01L29/66795 , H01L29/66818 , H01L29/66825 , H01L29/785 , H01L29/7856 , H01L29/7881
摘要： A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.
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4.发明公开METHOD OF FORMING SELF-ALIGNED SPLIT-GATE MEMORY CELL ARRAY WITH METAL GATES AND LOGIC DEVICES 审中-公开用金属栅极和逻辑器件形成自对准分裂栅极存储器单元阵列的方法
公开(公告)号：EP3248214A1
公开(公告)日：2017-11-29
申请号：EP16709160.2
申请日：2016-01-21
发明人： YANG, Jeng-Wei , CHEN, Chun-Ming , WU, Man-Tang , ZHOU, Feng , LIU, Xian , SU, Chien-Sheng , DO, Nhan
IPC分类号： H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/115
CPC分类号： H01L27/11524 , H01L21/28273 , H01L21/30604 , H01L27/11536 , H01L29/42328 , H01L29/66545 , H01L29/66825 , H01L29/7881
摘要： A method of forming a memory device by forming spaced apart first and second regions with a channel region therebetween, forming a floating gate over and insulated from a first portion of the channel region, forming a control gate over and insulated from the floating gate, forming an erase gate over and insulated from the first region, and forming a select gate over and insulated from a second portion of the channel region. Forming of the floating gate includes forming a first insulation layer on the substrate, forming a first conductive layer on the first insulation layer, and performing two separate etches to form first and second trenches through the first conductive layer. A sidewall of the first conductive layer at the first trench has a negative slope and a sidewall of the first conductive layer at the second trench is vertical.
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5.发明公开
公开(公告)号：EP3815149A1
公开(公告)日：2021-05-05
申请号：EP19799678.8
申请日：2019-04-09
发明人： DO, Nhan , SU, Chien-Sheng , YANG, Jeng-Wei
IPC分类号： H01L29/66 , H01L29/788
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6.发明授权
公开(公告)号：EP3357092B1
公开(公告)日：2020-09-30
申请号：EP16753518.6
申请日：2016-08-02
发明人： ZHOU, Feng , LIU, Xian , YANG, Jeng-Wei , SU, Chien-Sheng , DO, Nhan
IPC分类号： H01L29/423 , H01L29/788 , H01L29/66
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公开(公告)号：EP3243219B1
公开(公告)日：2019-06-26
申请号：EP15798284.4
申请日：2015-11-06
发明人： CHEN, Chun-Ming , WU, Man-Tang , YANG, Jeng-Wei , SU, Chien-Sheng
IPC分类号： H01L29/423 , H01L27/11521 , H01L29/66 , H01L29/788 , G11C16/04 , H01L21/28
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公开(公告)号：EP3497723A1
公开(公告)日：2019-06-19
申请号：EP17839956.4
申请日：2017-05-18
发明人： SU, Chien-Sheng , YANG, Jeng-Wei , WU, Man-Tang , CHEN, Chun-Ming , TRAN, Hieu Van , DO, Nhan
IPC分类号： H01L27/115 , H01L21/28 , H01L29/41 , H01L29/66 , H01L29/788
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9.发明授权
公开(公告)号：EP3248220B1
公开(公告)日：2019-03-06
申请号：EP16702642.6
申请日：2016-01-19
发明人： WU, Man-Tang , YANG, Jeng-Wei , SU, Chien-sheng , CHEN, Chun-Ming , DO, Nhan
IPC分类号： H01L27/115 , H01L29/423
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公开(公告)号：EP3326204A1
公开(公告)日：2018-05-30
申请号：EP16744931.3
申请日：2016-06-14
发明人： SU, Chien-sheng , YANG, Jeng-Wei , ZHOU, Feng
IPC分类号： H01L29/423 , H01L29/66 , H01L29/788 , H01L27/115
CPC分类号： H01L27/11531 , H01L27/11521 , H01L27/11524 , H01L29/42328 , H01L29/66484 , H01L29/66825 , H01L29/7881
摘要： A method of forming split gate non-volatile memory cells on the same chip as logic and high voltage devices having HKMG logic gates. The method includes forming the source and drain regions, floating gates, control gates, and the poly layer for the erase gates and word line gates in the memory area of the chip. A protective insulation layer is formed over the memory area, and an HKMG layer and poly layer are formed on the chip, removed from the memory area, and patterned in the logic areas of the chip to form the logic gates having varying amounts of underlying insulation.
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