公开(公告)号：EP0128624A3

公开(公告)日：1987-12-02

申请号：EP84200816

申请日：1984-06-08

Applicant: Philips Patentverwaltung GmbH ,  N.V. Philips' Gloeilampenfabrieken

Inventor： Kittel, Ludwig, Dr.

IPC: H04L07/04 ,  H04L01/10

CPC classification number: H04L7/048 ,  H04L1/0057

Abstract: In einem Datenübertragungssystem können Daten, ins besondere Meldungen, in Form von aneinander gereihten modifizierten Codewörtern einem linearen Blockcode über tragen werden. Die modifizierten Codewörter entstehen durch die Verknüpfung der aus den Daten gebildeten Code wörtern mit einem Schutzwort.
Bei bitweiser Verschachtelung von modifizierten Code wörtern können nach Entschachtelung auf der Empfangs seite vertauschungen in der Reihenfolge der Codewörter einer Meldung durch Bitverschiebung auftreten. Um die Er kennung einer Fehlsynchronisation zu ermöglichen, wird jedes Codewort mit einem seiner Position innerhalb der Meldung kennzeichnenden Schutzwort verknüpft. Die so entstehenden modifizierten Codewörter werden bitweise verschachtelt, übertragen und wieder entschachtelt und je des so entstehende Wort wird auf der Empfangsseite mit ei nem seiner Position innerhalb der Meldung kennzeichnen den Prüfwort verknüpft. Die Schutzwörter und Prüfwörter werden dabei so gewählt, dass die durch deren Verknüp fung gebildeten Schlüsselwörter vorzugsweise in Neben klassen liegen, welche nicht für die Decodierung verwendet werden.

公开(公告)号：EP0117756A3

公开(公告)日：1987-08-19

申请号：EP84301277

申请日：1984-02-27

Applicant: NEC CORPORATION

Inventor： Kaneko, Takashi

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1876

Abstract: The circuit (21) implements a known interpolation algorithm processing words flagged (F n , F n+1 ) as in error or correct. A correct word is passed on unchanged. An incorrect word is replaced by the means of the most recent correct word and the ensuing word, if that be correct, whereas it is replaced by the most recent correct word if the ensuing word is also incorrect. In order to avoid the complexity of known circuits with multiple latches and a complex output multiplexer, the words are written selectively into two address locations (a, β) in a RAM 15 in such a way that an adder 16 is always able to furnish the desired result to an output latch (17).

公开(公告)号：EP0117287A3

公开(公告)日：1987-02-25

申请号：EP83111128

申请日：1983-11-08

Applicant: International Business Machines Corporation

Inventor： Patel, Arvind Motibhai

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1809 ,  H03M13/15

Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).

公开(公告)号：EP0112988A3

公开(公告)日：1987-02-04

申请号：EP83110500

申请日：1983-10-21

Applicant: International Business Machines Corporation

Inventor： Patel, Arvind Motibhai

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/151 ,  G11B20/1833

Abstract: A syndrome processing unit for a multibyte error correcting system includes logical circuitry for performing product operation on selected pairs of 8-bit syndrome bytes, and exclusive-OR operations on selected results of the product operations are selectively combined to define usable cofactors that correspond to coefficients of the error locator polynomial if the codeword contains less than the maximum number of errors for which the system has been designed.

公开(公告)号：EP0094671A3

公开(公告)日：1986-07-16

申请号：EP83104820

申请日：1983-05-16

Applicant: SONY CORPORATION

Inventor： Odaka, Kentaro ,  Sako, Yoichiro ,  Kojima, Yuichi ,  Nakano, Kenji ,  Moriwaki, Hisayoshi

IPC: G11B05/09 ,  H04L01/10 ,  G06F11/10

CPC classification number: G11B20/1809

Abstract: In the recording/reproducing of digital audio signals, errors are detected and corrected by using two parity words, one arranged at the center of the block formed of data words and the arranged at one end of the block. The probability that uncorrectable error will be present in the center of the block is relatively high, so placing the parity word there prevents loss of the more valuable data. Maximum correctable burst errors are determined by the length of the block, so placing the other parity word on the end of the block lengthens it and improves burst error correction. The parity words are arranged as indicated before adding a cyclic redundancy check (CRC) code to the data signal and then modulation coding the signal before recording. During playback, the reproduced signal is demodulated and the CRC code used to detect errors for which error pointers are generated. The reproduced data is read into memories (3,4) in accordance with generated addresses and the pointers prevent the writing in of words found to be in error, which error words are subsequently corrected if possible using parity codes originally encoded into the signals prior to recording.

公开(公告)号：EP0098082A3

公开(公告)日：1986-05-07

申请号：EP83303488

申请日：1983-06-16

Applicant: SONY CORPORATION

Inventor： Creed, David Morris ,  Ive, John Goodwin Spencer

IPC: G11B05/09 ,  H04L01/10

CPC classification number: G11B20/1809

Abstract: @ A method of detecting and correcting errors in digital audio signals comprises assembling digital data words each of which corresponds to a digital audio signal representing an analog audio sample into units of six data words, assembling with each unit six redundant words derived by exclusive-OR operations on the data word in each row and each column of the unit, assembling the data words and redundant words into sub-blocks and adding cyclic redundancy check code words to the sub-block, recording and reproducing each sub-block, after reproduction using the code words of each sub-block to add error flags to each word in the sub-block, re-forming the units and assembling with each reproduced unit syndromes derived by exclusive-OR operations on the data words and redundant words in each row in each column of the unit, comparing the syndromes and correcting the error flags in dependence on this comparison, deriving horizontal syndromes by exclusive-OR operations on the data words and redundant words in each row of the reproduced unit and where there is only a single word in a row flagged as being in error, correcting that error word using the horizontal syndrome, and deriving vertical syndromes by exclusive-OR operations on the data words and the redundant word in each column of the reproduced unit and where there is only a single word in that column in error, correcting that error word using the vertical syndrome.

公开(公告)号：EP0127984A3

公开(公告)日：1985-01-09

申请号：EP84303496

申请日：1984-05-23

Applicant: BRITISH TELECOMMUNICATIONS

Inventor： Gordon, John Ashley ,  King, Graham Kenneth

IPC: H04L01/10

CPC classification number: H04L1/0054 ,  H04L1/0041

Abstract: An improvement to a Viterbi-type decoder for decoding convolutional error-correcting codes whereby decisions regarding which predecessor state to a given state most probably corresponds to the best path terminating in that given state are stored in association with that given state and not in association with the best path. Paths are reconstructed by searching through such stored decisions. Such searches are used to recover a number, possibly greater than one of data symbols for later output from the decoder. The larger this number, the less frequently a search need be carried out.

公开(公告)号：EP0096109A3

公开(公告)日：1984-10-24

申请号：EP82109564

申请日：1982-10-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Nagumo, Masahide ,  Inagawa, June ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/151 ,  G06F7/724 ,  G06F7/726 ,  G11B20/1809

Abstract: An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ 1 and σ 2 and error patterns e, and e 2 . The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ 1 and σ 2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e 1 and e 2 . The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).

公开(公告)号：EP0096165A3

公开(公告)日：1984-10-17

申请号：EP83102308

申请日：1983-03-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Inagawa, Jun ,  Nagumo, Masahide ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: G06F7/726 ,  G06F1/0307 ,  G11B20/1809 ,  H03M13/15

Abstract: Data representing one element α i of a Galois field GF(2 m ) are stored in a first linear shift register (52), and data representing another element α j of the Galois field GF(2 m ) are stored in a second linear shift register (53). 2 m elements of Galois field GF(2 m ) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter (51) which includes a decoder (511) and an encoder (512). The data representing element α j are supplied from the second linear shift register (53) to the decoder (511). If the data representing the reciprocal of element α j are stored in the converter (51), they are read from the encoder (512). If they are not stored in the converter (51), the first linear shift register (52) and the second linear shift register (63) are shifted N times by control pulses generated by a NOR gate (NOR,) and an AND gate (AND, o ) until any one of the reciprocal data are read from the encoder (512), whereby the register (52) supplies data representing α i+N and the register (53) supplies data representing α -(j+N) . A multiplier (54) multiplies element α i by reciprocal α j or multiplies element α 1+N by reciprocal α -(j+N) , thereby performing the division: a i ÷ α j (= α i-j ).

公开(公告)号：EP0096163A3

公开(公告)日：1984-10-17

申请号：EP83102173

申请日：1983-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Inagawa, Jun ,  Nagumo, Masahide ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/15 ,  G06F7/726 ,  G11B20/1809

Abstract: An apparatus divides one element a' of a Galois field GF(2 m ) by another element α i of the field. Divider data α i are supplied to one of the first linear shift registers (A, to A4) and to the other first linear shift registers through α N1 , α N2 ,... multiplier circuits (51 to 53), respectively. Simultaneously, dividend data α i are supplied to one of the second linear shift registers (B, to B 4 ) and to the other second linear shift registers through α N1 , α N2 , ... multiplier circuits (58 to 60), respectively. "1" detector circuits (55 to 57) are connected to the outputs of the first linear shift registers (A, to A 4 ), respectively. The first linear shift registers (A, to A4) and the second linear shift registers (B 1 to B 4 ) are shifted several times until any "1" detector circuit (55 to 57) detects "1' in response to output signals from a 2-input AND gate (AND,,). When "1" is detected, a NOR gate (NOR, o ) supplies a signal of logical "0" to the AND gate (AND,,), whereby the AND gate (AND 11 ) stops supplying output signals. 2-input AND circuits (61 to 64) are connected at one input terminal to the outputs of the "1" detector circuits (54 to 57) and at the other input terminal to the outputs of the second linear shift registers (B, to B 4 ). The AND circuit connected to the "1" detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division α i - a i , are delivered through an OR circuit (65).