摘要:
A self-healing data network and network node controller. Data transmission of data cells to form messages permitting self-clocking operation of each node and elastic buffering implemented to allow receipt of messages without regard to the phase of messages allows asynchronous operation of each node relative to other nodes. Fault detection and network self-healing are performed by each node independently of other nodes.
摘要:
A data transmission system for the non-contact transmission of data between a station (1) and a portable data carrier (2). The station (1) includes a station transmitter (3) operating at a predetermined frequency for generating a first signal and a demodulator (35) for detecting a second signal superimposed on the first signal. An antenna (5) is coupled via a length of cable (4) to the station transmitter (3) via a matching circuit (6) so as to be operative at said frequency regardless of the length of the cable (4). The portable data carrier (2) includes supply means (13) for coupling to a source of electric power and a data carrier tuned antenna circuit (10, 55) inductively coupled with the station transmitter (3) so as to receive power from the station (1). A data carrier data modulator (14) is provided for modulating the first signal with the second signal in response to data stored within the data carrier (2) and, by means of said inductive coupling, enabling the data to be transmitted from the data carrier (2) to the station (1).
摘要:
Dans la microplaquette émettrice, les bits sont sérialisés et appliqués à un codeur dans lequel le train de bits (D) et son complément ( D ) sont transformés en deux signaux (PH1 et PH2) sous contrôle d'un signal d'horloge en dents de scie CK'. Les signaux (PH1 et PH2) sont envoyés à la microplaquette réceptrice, les signaux (PH1 et PH2) sont appliqués à un décodeur qui engendre deux signaux ( DJ ) et (DK) représentatifs des bits de données et un signal d'horloge CLK reconstitué. Les trois signaux ( DJ , DK et CLK) ainsi qu'un signal de trame (F) sont utilisés par un circuit de conversion et de démultiplexage pour retrouver les multiplets de bits de données parallèles.
摘要:
Es wird eine Möglichkeit vorgestellt, wie Takt und Daten aus einem im Bi-Phase-Code übertragenen Datenstrom rückgewonnen werden können, auch wenn der Datenstrom keine Synchronisierbits enthält und seine Übertragungsgeschwindigkeit schwankt. Zur Taktrückgewinnung wird ein nicht nachtriggerbares Monoflop bei jedem Phasenwechsel angesteuert. Die zwischengeschobenen Phasenwechsel werden dadurch in ihrer Auswirkung unterdrückt. Mit dem Takt wird ein Speicher angesteuert, der zum richtigen Zeitpunkt die gültigen Daten aus dem übertragenen Datenstrom übernimmt und während je einer Taktzeit konstant hält.
摘要:
In a wireless infrared communications system, a technique for encoding data for serial transmission and the correlative technique for decoding the transmitted data. A data transmission period is divided into a plurality of slots. In a given pair of slots, the first slot comprises a gray code sequence of bits and a check bit, and the second slot comprises the same gray code sequence of bits and the complement of the check bit in the first slot. The last slot in a transmission time period comprises a guard slot to separate transmission time periods. A decoder receives the encoded data, and for a given slot derives calculated data for the slot from the gray code sequence of bits and the check bit. The check bit for the given slot is compared with a calculated check bit of the previous slot to determine if a predetermined relationship exists. If the predetermined relationship exists, the received encoded data is selected as the output of the decoder, and if the predetermined relationship does not exist, the calculated data is selected as the output of the decoder. The calculated check bit is derived from the output of the decoder for a slot, and is compared with the check bit of the encoded data for the following slot.
摘要:
A digital loop filter translates a multi-bit phase error input into a high resolution control signal utilizable as an advance-retard control for a multi-phase clock generator. The digital filter couples the multi-bit phase error input to the clock generator via a pulse density modulation (PDM) accumulator, providing multi-phase adjustment in a single sample clock cycle based on the overflow or underflow of the PDM accumulator. Variable PDM cycles are used to control loop filter bandwidth, permitting adjustable capture sequences. Thus, real proportional control of the multi-phase clock generator is limited only by the word size of the phase error input.