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139 条记录 (耗时 0.027 秒)

    APPARATUS FOR GLITCHLESS CLOCK DIVIDER WITH FAST CLOCK CHANGE AND METHOD THEREOF
    23.
    发明公开
    APPARATUS FOR GLITCHLESS CLOCK DIVIDER WITH FAST CLOCK CHANGE AND METHOD THEREOF 审中-公开
    装置上使用快速时钟变化及其方法无故障时钟分频

    公开(公告)号：EP2718780A1

    公开(公告)日：2014-04-16

    申请号：EP11867485.2

    申请日：2011-06-09

    申请人： Nokia Corporation

    发明人： HATULA, Ari ,  PENNALA, Jussi

    IPC分类号： G06F1/08 ,  G06F1/06 ,  H03K23/00

    CPC分类号： G06F1/08 ,  G06F1/06 ,  H03K23/667

    摘要： An apparatus comprising a clock shaper (510) configured to derive a frequency of a reference clock signal (501) into a plurality of n frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1,..., Clock n-1 (571-0, 571-1,..., 571-n-1), and configured to generate a plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m), where n is a number of the gated clocks and m corresponds to a divisor; a plurality of n coupled clock selection and gating units (550-0, 550-1,..., 550-n-1) receiving the reference clock (501) and the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m), and configured to select one of the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m) and to gate to an output clock (571-0, 571-1,..., 571-n-1); and a phase decoding unit (530) configured to decode the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m) based on a plurality of received division value per clock signals, and configured to generate a plurality of n clock selection signals (531-0, 531-1,..., 531-n-1), wherein one of the plurality of n clock selection signals (531-0, 531-1 531 -n-1) corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks (571-1, 571-2,..., 571-n-1); wherein the plurality of n coupled clock selection and gating units (550-0, 550-1 550-n-1) are responsive to the plurality of n clock selection signals (531-0, 531-1 531 -n-1) to generate the output clock (571-0, 571-1,..., 571 -n-1) with the selected frequency.

    A/D CONVERTING CIRCUIT, SOLID-STATE IMAGE SENSING DEVICE AND CAMERA SYSTEM
    26.
    发明公开
    A/D CONVERTING CIRCUIT, SOLID-STATE IMAGE SENSING DEVICE AND CAMERA SYSTEM 有权
    A / D-WANDLERSCHALTUNG，FESTKÖRPERBILDERFASSUNGSGERÄTUND KAMERASYSTEM

    公开(公告)号：EP2197118A1

    公开(公告)日：2010-06-16

    申请号：EP08834294.4

    申请日：2008-09-25

    申请人： Sony Corporation

    发明人： HISAMATSU, Yasuaki

    IPC分类号： H03M1/56 ,  H03K23/00 ,  H04N5/335

    CPC分类号： H04N5/363 ,  H03K23/62 ,  H03M1/1023 ,  H03M1/12 ,  H03M1/123 ,  H03M1/1295 ,  H03M1/20 ,  H03M1/56 ,  H04N5/335 ,  H04N5/378

    摘要： There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC 15A is configured as an integrating-type A/D conversion circuit using a comparator 151 and a counter 152. The counter 152 has a function of switching a count mode from an up count to a down count and from a down count to an up count while a value is held, a function of performing counting at both rising and falling edges of an input clock CK at a frequency two times as high as that of the input clock, and a function of latching the input clock CK in accordance with an output signal of the comparator 151 and setting non-inverted or inverted data of the latched data to be data of an LSB.

    摘要翻译： 提供了一种A / D转换电路，其中计数器能够在时钟的两个边缘进行计数，可以在保持上/下计数值时切换上/下计数值，并且 即使使用双边计数，固态图像传感器和照相机系统，计数操作也难以失真。 ADC 15A被配置为使用比较器151和计数器152的积分型A / D转换电路。计数器152具有将计数模式从上计数切换到递减计数和从向下计数切换到 在保持值的同时计数，在输入时钟CK的上升沿和下降沿以与输入时钟的两倍的频率进行计数的功能，以及根据输入时钟CK锁存输入时钟CK的功能 比较器151的输出信号，并将锁存数据的非反转或反相数据设置为LSB的数据。

    METHOD FOR COUNTING BEYOND ENDURANCE LIMITATIONS OF NON-VOLATILE MEMORIES
    27.
    发明授权
    METHOD FOR COUNTING BEYOND ENDURANCE LIMITATIONS OF NON-VOLATILE MEMORIES 有权
    程序统计关于耐久性RESTRICTIONS非易失性存储器AWAY

    公开(公告)号：EP1588320B1

    公开(公告)日：2007-05-09

    申请号：EP03815650.1

    申请日：2003-12-16

    申请人： ATMEL CORPORATION

    发明人： MALETSKY, Kerry, D.

    IPC分类号： G06M3/00 ,  H03K21/40 ,  H03K23/00

    CPC分类号： H03K21/403 ,  G11C16/102 ,  G11C16/349 ,  H03K23/005

    摘要： A digital counter (e.g., Fig. 1) that uses non-volatile memories (12, 14, 16, 18, ...) as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter (20, 22) that keeps track of the less significant part of the count and a binary counter (10) that keeps track of the more significant part of the count. The rotary counter implements a counting method that maximizes the count that can be obtained before the endurance limit of the memory is reached by making sure that each change of state of each cell is recorded as one count and that all cells in the rotary counter experience two change of state in every cycle. The binary counter (10) records the number of cycles the rotary counter has gone through.