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公开(公告)号：EP2936303B1
公开(公告)日：2020-01-15
申请号：EP13821338.4
申请日：2013-12-20
IPC分类号： G06F12/0864 , G06F9/38 , G06F12/0875
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公开(公告)号：EP3475808A1
公开(公告)日：2019-05-01
申请号：EP17729733.0
申请日：2017-06-06
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公开(公告)号：EP3335108A1
公开(公告)日：2018-06-20
申请号：EP16742126.2
申请日：2016-07-11
发明人： MAHURIN, Eric Wayne , CODRESCU, Lucian , PLONDKE, Erich James , HOYLE, David , ZENG, Mao , GAN, Kim-Chyan
IPC分类号： G06F9/30
摘要： Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.
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公开(公告)号：EP2577464B1
公开(公告)日：2017-08-16
申请号：EP11726254.3
申请日：2011-05-23
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5.发明授权SHARED INTERRUPT CONTROL METHOD AND SYSTEM FOR A DIGITAL SIGNAL PROCESSOR 有权共享中断 - 维护者系统FÜREINEN DIGITALEN信号检测器
公开(公告)号：EP1941352B1
公开(公告)日：2017-04-26
申请号：EP06826211.2
申请日：2006-10-18
CPC分类号： G06F9/4812 , G06F9/30101 , G06F9/3851
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公开(公告)号：EP2260388B1
公开(公告)日：2016-08-31
申请号：EP09714236.8
申请日：2009-02-03
IPC分类号： G06F12/12
CPC分类号： G06F12/0808 , G06F12/121 , G06F2212/1016 , Y02D10/13
摘要： A system for determining a cache line to replace is described. In one embodiment, the system includes a cache comprising a plurality of cache lines. The system further includes an identifier configured to identify a cache line for replacement. The system also includes a control logic configured to determine a value of the identifier selected from an incrementer, a cache maintenance instruction, or remains the same.
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公开(公告)号：EP2972898A1
公开(公告)日：2016-01-20
申请号：EP14729747.7
申请日：2014-03-11
发明人： KOOB, Christopher, Edward , PLONDKE, Erich, James , PATEL, Piyush , SARTORIUS, Thomas, Andrew , CODRESCU, Lucian
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F12/1009 , G06F12/109 , G06F2212/1008 , G06F2212/1048 , G06F2212/1052 , G06F2212/657
摘要： A method includes reading, by a processor, one or more configuration values from a storage device or a memory management unit. The method also includes loading the one or more configuration values into one or more registers of the processor. The one or more registers are useable by the processor to perform address translation.
摘要翻译： 一种方法包括由处理器从存储设备或存储器管理单元读取一个或多个配置值。 该方法还包括将一个或多个配置值加载到处理器的一个或多个寄存器中。 一个或多个寄存器可由处理器执行地址转换。
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公开(公告)号：EP2232370B1
公开(公告)日：2015-11-04
申请号：EP08856823.3
申请日：2008-12-03
CPC分类号： G06F9/526 , G06F9/30083 , G06F9/30101 , G06F12/1027 , G06F2209/522 , Y02D10/13
摘要： Systems and methods including a multithreaded processor with a lock indicator are disclosed. In an embodiment, a system includes means for indicating a lock status of a shared resource in a multithreaded processor. The system includes means for automatically locking the shared resource before processing exception handling instructions associated with the shared resource. The system further includes means for unlocking the shared resource.
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9.发明公开USING THE LEAST SIGNIFICANT BITS OF A CALLED FUNCTION'S ADDRESS TO SWITCH PROCESSOR MODES 有权用最少的显著位的地址一个叫函数的处理器模式不断变化
公开(公告)号：EP2812792A1
公开(公告)日：2014-12-17
申请号：EP13706805.2
申请日：2013-02-07
发明人： TABONY, Charles Joseph , PLONDKE, Erich James , CODRESCU, Lucian , VENKUMAHANTI, Suresh K. , MENEZES, Evandro Carlos
CPC分类号： G06F9/30189 , G06F9/30054 , G06F9/30076 , G06F9/30149 , G06F9/30181 , G06F9/322 , G06F9/3816
摘要： Systems and methods for tracking and switching between execution modes in processing systems. A processing system is configured to execute instructions in at least two instruction execution modes including a first and second execution mode chosen from a classic/aligned mode and a compressed/unaligned mode. Target addresses of selected instructions such as calls and returns are forcibly misaligned in the compressed mode, such one or more bits, such as, the least significant bits (alignment bits) of the target address in the compressed mode are different from the corresponding alignment bits in the classic mode. When the selected instructions are encountered during execution in the first mode, a decision to switch operation to the second mode is based on analyzing the alignment bits of the target address of the selected instruction.
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10.发明公开
公开(公告)号：EP2758897A2
公开(公告)日：2014-07-30
申请号：EP12784364.7
申请日：2012-09-24
发明人： PLONDKE, Erich J. , CODRESCU, Lucian , ZENG, Mao , BALASUBRAMANIAN, Swaminathan , HOYLE, David J.
CPC分类号： G06F9/30021 , G06F7/544 , G06F9/30036 , G06F17/18
摘要： An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.
摘要翻译： 公开了一种确定极值的装置，系统和方法。 参考位置标识符和参考极值被耦合。 确定输入数据集的输入极值，并确定输入极值的相应位置标识符。 基于比较，将输入极值与参考极值进行比较，以确定输出极值和输出位置标识符。
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