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    COMMUTATION ASSISTANCE BY CONTROLLING THE SHAPE OF THE CURRENT WAVE IN A BIDIRECTIONAL TOTEM POLE CONVERTER
    31.
    发明公开
    COMMUTATION ASSISTANCE BY CONTROLLING THE SHAPE OF THE CURRENT WAVE IN A BIDIRECTIONAL TOTEM POLE CONVERTER 审中-公开

    公开(公告)号：EP4472050A1

    公开(公告)日：2024-12-04

    申请号：EP24315250.1

    申请日：2024-05-29

    Applicant: STMicroelectronics International N.V.

    Inventor： Hague, Yannick ,  Launois, Romain ,  Thiennot, Guillaume

    IPC: H02M1/42 ,  H02M7/162 ,  H02M1/12

    Abstract: A bidirectional PFC system includes a high-frequency branch with a first transistor connected between an IO node and a high-frequency tap, and a second transistor connected between the high-frequency tap and a reference node, and a low-frequency branch with a first thyristor connected between the IO node and a low-frequency tap, and a second thyristor connected between the low-frequency tap and the reference node. An inductor is connected between the first node and the high-frequency tap. A first capacitor is connected between the first node and the low-frequency tap. The first node and the low-frequency tap are coupled to input terminals. A control circuit generates first and second gate drive signals for the transistors so as to modify an AC signal at the input terminals such that the AC current falls below a holding current of the second thyristor prior to zero crossing of the AC voltage.

    PROCÉDÉ DE GESTION DU CYCLE DE VIE D'UN SYSTÈME SUR PUCE, ET SYSTÈME SUR PUCE CORRESPONDANT
    32.
    发明公开
    PROCÉDÉ DE GESTION DU CYCLE DE VIE D'UN SYSTÈME SUR PUCE, ET SYSTÈME SUR PUCE CORRESPONDANT 审中-公开

    公开(公告)号：EP4471644A1

    公开(公告)日：2024-12-04

    申请号：EP24176821.7

    申请日：2024-05-20

    Applicant: STMicroelectronics International N.V.

    Inventor： PALLARDY Loic ,  MERE, Maxime ,  JOUAULT, Frédéric

    IPC: G06F21/76

    Abstract: Le procédé de gestion du cycle de vie (LCMS) d'un système sur puce (SOC) ayant des fonctionnalités (IPS), comprenant une gestion de la propriété à plusieurs acteurs (MUOS) répertoriant des propriétaires des fonctionnalités dans un répertoire, et comprenant une allocation des droits d'une fonctionnalité (IPS) au cours du cycle de vie du système sur puce, en fonction d'une commande de configuration (CmdConfig) comportant une identification de ladite fonctionnalité, une identification d'un droit de propriété ou d'accès de la fonctionnalité, et une signature du propriétaire de cette fonctionnalité (SignST>, SignUser>).

    COMPRESSION-BASED SCAN TEST SYSTEM
    33.
    发明公开
    COMPRESSION-BASED SCAN TEST SYSTEM 审中-公开

    公开(公告)号：EP4467997A1

    公开(公告)日：2024-11-27

    申请号：EP24175044.7

    申请日：2024-05-09

    Applicant: STMicroelectronics International N.V.

    Inventor： JAIN, Sandeep ,  PATHAK, Shalini ,  SINGH, Prateek

    IPC: G01R31/3183 ,  G01R31/3185 ,  G01R31/317 ,  G01R31/3181

    Abstract: In accordance with an embodiment, a method for operating a Pseudo-Random Pattern Generator, PRPG, (104) based scan test system includes: generating (402) test patterns using a Pseudo-Random Pattern Generator, PRPG, (104), generating the test patterns including clocking the PRPG (104) using a first clock signal (CLK1); loading (404) the test patterns into a plurality of scan chains (116) coupled to the PRPG (104); modifying (406) a bit distribution of the generated test patterns with respect to the plurality of scan chains (116) by freezing at least one clock cycle of the first clock signal (CLK1) while a second clock signal (CLK2) is active or freezing at least one clock cycle of the second clock signal (CLK2) while the first clock signal (CLK1) is active; shifting (408) the loaded test patterns using the second clock signal (CLK2); applying the test patterns to a circuit under test, CUT, (112) through the plurality of scan chains (116); and capturing (412) response patterns generated by the CUT (112) in the plurality of scan chains (116).

    USE OF MONOLITHIC WIRELESS TRANSMITTER WITH SWITCHED CAPACITOR CONVERTER TO DESIGN HEATER FOR E-CIGARETTE
    35.
    发明公开
    USE OF MONOLITHIC WIRELESS TRANSMITTER WITH SWITCHED CAPACITOR CONVERTER TO DESIGN HEATER FOR E-CIGARETTE 审中-公开

    公开(公告)号：EP4456667A1

    公开(公告)日：2024-10-30

    申请号：EP24169867.9

    申请日：2024-04-12

    Applicant: STMicroelectronics International N.V.

    Inventor： LEONG, Foo Leng ,  LI, Yanlei ,  YANG, Wanli

    IPC: H05B6/06 ,  H05B6/10

    Abstract: Disclosed herein is an electronic device (10) including a switched capacitor circuit (102) generating a boosted voltage (Vboost) from a battery voltage (Vbatt) and a monolithic transmitter (103) integrated within a single integrated circuit substrate (103). The monolithic transmitter includes a bridge (104) powered between the boosted voltage and a reference voltage and is operated based upon bridge control signals (HS_AC1, LS_AC1, HS_AC2, LS_AC2) generated by a digital core (105) within the monolithic transmitter. A tank capacitor (Ctank) and a coil (112) are series connected between output nodes of the bridge. During operation, the monolithic transmitter causes generation of a time-varying magnetic field about the coil, in turn inducing eddy currents in a workpiece (1122) disposed within the time-varying magnetic field to thereby heat the workpiece.

    NFC CONTROLLER
    36.
    发明公开
    NFC CONTROLLER 审中-公开

    公开(公告)号：EP4456439A1

    公开(公告)日：2024-10-30

    申请号：EP24170141.6

    申请日：2024-04-15

    Applicant: STMicroelectronics International N.V.

    Inventor： GRUNDRICH, Christophe ,  KOVACIC, Kosta ,  LEDUC, Bruno

    IPC: H04B5/72 ,  H04B5/79 ,  H02J7/34

    Abstract: The present disclosure relates to an NFC controller comprising a first node (NVBAT) configured to be coupled to a battery; a second node (NVDD_TX) configured to receive a regulated voltage from an external dc/dc converter coupled to said first node ; a third node (RF01, RF02) configured to be coupled to an radiofrequency output of the NFC controller; said third node been configured to, in a first mode, be coupled either to the first or second nodes, and in a second mode, either to the first node or to first and second nodes.

    SEMICONDUCTOR PACKAGE, METHOD OF FORMING SEMICONDUCTOR PACKAGE, AND POWER MODULE
    37.
    发明公开
    SEMICONDUCTOR PACKAGE, METHOD OF FORMING SEMICONDUCTOR PACKAGE, AND POWER MODULE 审中-公开

    公开(公告)号：EP4456132A1

    公开(公告)日：2024-10-30

    申请号：EP24171773.5

    申请日：2024-04-23

    Applicant: Shenzhen STS Microelectronics Co., Ltd. ,  STMicroelectronics International N.V.

    Inventor： LIU, Qian ,  TIZIANI, Roberto

    IPC: H01L23/64 ,  H01L23/31 ,  H01L25/07 ,  H01L23/48

    Abstract: Embodiments of the present disclosure relate to a semiconductor package, a method of forming semiconductor package and a power module. For example, there is provided a semiconductor package. The semiconductor package may comprise a chip level having a first side and a second side opposite to the first side, wherein the chip level comprises a plurality of power transistors and each power transistor is provided with a source and a gate at the first side. Besides, the semiconductor package may also comprise a first conductive level positioned on the first side and comprising a gate connection portion electrically connected with the gate and a source connection portion electrically connected with the source. The semiconductor package further comprises a second conductive level comprising a gate lead-out portion electrically connected with the gate connection portion and a source lead-out portion electrically connected with the source connection portion, wherein the first conductive level is positioned between the second conductive level and the chip level. Embodiments of the present disclosure may enhance the working performance of the product by improving consistency of conductive paths from the gate and the source of each power transistor to corresponding points.

    DELTA-SIGMA MODULATOR WITH ANTI-WINDUP CIRCUIT
    38.
    发明公开
    DELTA-SIGMA MODULATOR WITH ANTI-WINDUP CIRCUIT 审中-公开

    公开(公告)号：EP4451568A1

    公开(公告)日：2024-10-23

    申请号：EP24163598.6

    申请日：2024-03-14

    Applicant: STMicroelectronics International N.V.

    Inventor： STILGENBAUER, Francesco ,  BOTTI, Edoardo ,  MALCOVATI, Piero ,  CROVETTI, Paolo Stefano ,  BONIZZONI, Edoardo ,  DE FERRARI, Matteo

    IPC: H03M3/00 ,  H03M7/32

    Abstract: A delta-sigma modulator (110) includes a loop filter circuit (114) having a first input that receives an input signal (102) and a second input that receives a feedback signal (105). The loop filter (114) circuit generates a filtered signal (106). A quantizer circuit (124) quantizes the filtered signal (106) to generate an output signal (103). An anti-windup circuit (112) detects instances where the filtered signal (106) is outside an input signal input of the quantizer circuit (124) and in response thereto generates a dead zone signal (107) having a magnitude and sign corresponding to a difference between the filtered signal and the input signal range. The feedback signal (105) is a sum of the output signal (103) and the dead zone signal (107).

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