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    INTEGRATED MILLIMETER WAVE ANTENNA ESD PROTECTION
    3.
    发明公开
    INTEGRATED MILLIMETER WAVE ANTENNA ESD PROTECTION 审中-公开

    公开(公告)号：EP4456320A1

    公开(公告)日：2024-10-30

    申请号：EP23216209.9

    申请日：2023-12-13

    申请人： INTEL Corporation

    发明人： GOSSNER, Harald ,  WAGNER, Thomas ,  WAIDHAS, Bernd ,  SEIDEMANN, Georg ,  YANG, Tae Young ,  KAMGAING, Telesphor

    IPC分类号： H01Q1/22 ,  H01Q1/38 ,  H01Q1/48 ,  H01Q9/04 ,  H01L23/60 ,  H01L23/64 ,  H01L23/66

    摘要： An antenna device includes an antenna on a substrate, a low-impedance electrostatic discharge (ESD) path for an ESD pulse from the antenna to a ground terminal, and a signal path between the antenna and either a signal terminal or an integrated circuit (IC) die. The ESD and signal paths may each include separate vias through the substrate. A capacitor may couple a signal to or from the antenna and the signal terminal (or IC die) but block low-frequency power (such as an ESD pulse). The ESD path has an electrical length of a quarter of the wavelength and so may present a high impedance to ground for the signal. The antenna device may include or be coupled to an IC die. The IC die may couple to the signal and ground terminals, e.g., opposite the substrate from the antenna.

    HIGH VOLTAGE INTEGRATED CIRCUIT PACKAGES WITH DIAGONALIZED LEAD CONFIGURATIONS
    4.
    发明公开
    HIGH VOLTAGE INTEGRATED CIRCUIT PACKAGES WITH DIAGONALIZED LEAD CONFIGURATIONS 审中-公开

    公开(公告)号：EP4456131A1

    公开(公告)日：2024-10-30

    申请号：EP24160646.6

    申请日：2024-02-29

    申请人： Allegro MicroSystems, LLC

    发明人： Salato, Maurizio ,  Taylor, William P.

    IPC分类号： H01L23/64 ,  H01L23/50 ,  H01L23/495

    摘要： Aspects of the present disclosure include systems, structures, circuits, and methods providing integrated circuit (IC) packages or modules having diagonalized leads. First and second semiconductor dies are disposed on a substrate. First and second coils are configured on the substrate for a transformer. The transformer may include a core. The leads or pins may be aligned along a diagonal of the package body, providing increased creepage. The IC packages and modules may include various types of circuits; in some examples, IC packages or modules may include a galvanically isolated gate driver or other high voltage circuit.

    ON-CHIP MULTI-LAYER TRANSFORMER AND INDUCTOR
    8.
    发明公开
    ON-CHIP MULTI-LAYER TRANSFORMER AND INDUCTOR 审中-公开

    公开(公告)号：EP4290575A3

    公开(公告)日：2024-03-06

    申请号：EP23204860.3

    申请日：2018-03-30

    申请人： INTEL Corporation

    发明人： YU, Chuanzhao ,  LI, Qiang ,  NEWMAN, David

    IPC分类号： H01F27/28 ,  H01F17/00 ,  H01F41/04 ,  H01F27/34 ,  H01F19/04 ,  H01L23/64 ,  H01L23/66

    摘要： An inductance apparatus, including: a first winding including a first wire section and a second wire section, the first wire section and the second wire section are disposed parallel to each other in a first horizontal plane associated with a center axis, and the first winding associated with an equivalent current flow path within the first horizontal plane; and a second winding to extend around the center axis in the first horizontal plane between the first wire section and the second wire section, wherein the equivalent current flow path of the first winding is aligned with a current flow path associated with the second winding.

    CHIP STRUCTURE AND WIRELESS COMMUNICATION DEVICE
    10.
    发明公开
    CHIP STRUCTURE AND WIRELESS COMMUNICATION DEVICE 审中-公开

    公开(公告)号：EP4318582A2

    公开(公告)日：2024-02-07

    申请号：EP23188369.5

    申请日：2019-12-18

    申请人： Huawei Technologies Co., Ltd.

    发明人： FAN, Jinhan ,  CHI, Yusong ,  ZHU, Nianyong

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/64 ,  H01L23/66 ,  H01L23/00 ,  H10N97/00 ,  H03F3/195

    摘要： A chip structure is provided, including a die, a first chip bond pad, and a second chip bond pad. A first radio frequency module, a second radio frequency module, a first interconnect metal wire, and a second interconnect metal wire are disposed in the die. The first interconnect metal wire is connected to the first radio frequency module, and is configured to provide an alternating current ground for the first radio frequency module. The second interconnect metal wire is connected to the second radio frequency module, and is configured to provide an alternating current ground for the second radio frequency module. The first chip bond pad and the second chip bond pad are disposed on a surface of the die. The first chip bond pad is connected to the first interconnect metal wire, the second chip bond pad is connected to the second interconnect metal wire, and the first chip bond pad with the first interconnect metal wire and the second chip bond pad with the second interconnect metal wire are isolated from each other. According to the foregoing technical solution, a path through which a crosstalk signal between the first radio frequency module and the second radio frequency module propagates through the alternating current grounds is greatly extended, thereby improving isolation of a chip.