公开(公告)号：EP0582827A2

公开(公告)日：1994-02-16

申请号：EP93110651.2

申请日：1993-07-03

申请人： GENERAL INSTRUMENT CORPORATION OF DELAWARE

发明人： Paik, Woo H. ,  Fox, John M. ,  Lery, Scott A.

IPC分类号： H03M13/22 ,  H03M13/12 ,  H04L7/04 ,  H03M13/00

CPC分类号： H03M13/2732 ,  H03M13/33

摘要： An interleaver (34) processes information in a pseudorandom order to provide pseudorandom interleaved data for communication to a deinterleaver (42). The pseudorandom interleaved data is processed at the deinterleaver (42) in a pseudorandom order corresponding to that used at the interleaver (34) means, to recover the original information. The pseudorandom processing at the deinterleaver is synchronized with the pseudorandom processing at the interleaver on a trial and error basis. In one embodiment, full synchronization occurs when a Viterbi decoder (44) receiving data from the deinterleaver has a renormalization rate within a designated threshold and when enough synchronization words are detected in data output from the deinterleaver to meet a predetermined criterion. In another embodiment, a timer is used to initiate a new starting address for the pseudorandom processing at the deinterleaver during successive time intervals. Synchronization is achieved when a start address is found that results in the detection of enough synchronization words in data output from the deinterleaver to meet a predetermined synchronization criterion.

摘要翻译： 交织器（34）以伪随机顺序处理信息以提供用于与解交织器（42）进行通信的伪随机交织数据。 在去交错器（42）以与交织器（34）装置上使用的伪随机顺序相对应的伪随机顺序处理伪随机交织的数据，以恢复原始信息。 解交织器上的伪随机处理与在交织器上的伪随机处理以试错法同步。 在一个实施例中，当从解交织器接收数据的维特比解码器（44）在指定阈值内具有重正化率并且当从解交织器输出的数据中检测到足够的同步字以满足预定标准时，发生完全同步。 在另一个实施例中，定时器用于在连续时间间隔期间在解交织器处启动用于伪随机处理的新起始地址。 当发现起始地址导致从解交织器输出的数据中检测足够的同步字以满足预定的同步标准时，实现同步。

公开(公告)号：EP0562422A1

公开(公告)日：1993-09-29

申请号：EP93104294.9

申请日：1993-03-16

申请人： GENERAL INSTRUMENT CORPORATION OF DELAWARE

发明人： Paik, Woo H. ,  Lery, Scott A. ,  Fox, John M.

IPC分类号： H04L27/00

CPC分类号： H04L1/0059 ,  H04L1/0071 ,  H04L27/0012 ,  H04N5/211

摘要： A quadrature amplitude modulation (QAM) communication system is provided in which data can be communicated in any one of a plurality of QAM modes, such as 16-QAM, 32-QAM, and 64-QAM (30). A receiver (70) detects the particular QAM mode transmitted on a trial and error basis, by attempting to decode the received data using different QAM modes until a synchronization condition is detected. The synchronization condition can require that a plurality of different synchronization tests be met. In a specific embodiment, a first synchronization test is met when a renormalization rate of a trellis decoder (90) is below a threshold value. A second synchronization test is met when a first synchronization word is detected in the received data. A third and final synchronization test is met when a second synchronization word is detected in the received data. In order to reduce the cost of the receiver, most of the QAM mode dependent components (76, 80, 84, 90, 98, 102) are implemented using look-up tables stored in PROMs.

摘要翻译： 提供了一种正交幅度调制（QAM）通信系统，其中数据可以以诸如16-QAM，32-QAM和64-QAM（30）的多个QAM模式中的任何一个传送。 接收机（70）通过尝试使用不同的QAM模式对接收到的数据进行解码直到检测到同步状态来检测基于试错法传输的特定QAM模式。 同步条件可以要求满足多个不同的同步测试。 在具体实施例中，当网格解码器（90）的重正化率低于阈值时，满足第一同步测试。 当在所接收的数据中检测到第一同步字时，满足第二同步测试。 当在所接收的数据中检测到第二同步字时，满足第三次和最后的同步测试。 为了降低接收机的成本，使用存储在PROM中的查找表来实现大多数QAM模式相关组件（76,80,84,90,98,102）。

公开(公告)号：EP0543197A2

公开(公告)日：1993-05-26

申请号：EP92118660.7

申请日：1992-10-31

申请人： GENERAL INSTRUMENT CORPORATION OF DELAWARE

发明人： Shen, Paul ,  Paik, Woo H. ,  Krause, Edward A.

IPC分类号： G11C7/00 ,  G11C11/409

CPC分类号： G11C7/1075 ,  G11C7/1036 ,  H04N19/423 ,  H04N19/433 ,  H04N19/51 ,  H04N19/61

摘要： A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

摘要翻译： 本发明提供一种多串行存取存储器。 一种动态随机存取存储器（30）被从写给向其输入数据和输出数据在那里。 数据行是从在响应所述阵列（50），以解决信号（34，36，38）提供给它的输出。 的串行输出端口（44，46，48）的多个耦合到所述阵列的输出用于选择性地从阵列锁存数据输出的不同的行。 串行输出端口（44，46，48）从时钟到输出锁存的数据在那里。 在图示的实施例中，每个串行输出端口的包含具有等于所述存储器阵列（30）的宽度的长度的移位寄存器（62，64，66，... 68）。 移位寄存器响应于从所述阵列（30）闩锁的一行数据的第一定时信号（42，52）。 第二定时信号致动所述移位寄存器移位锁存一行数据。 耦合到所述移位寄存器的串行访问选择器（70）输出从串行输出端口的移位的数据的所选部分，所述存储器具有特别的应用为帧存储器，用于运动补偿的帧间图像编码/解码系统。

公开(公告)号：EP0524559A2

公开(公告)日：1993-01-27

申请号：EP92112305.5

申请日：1992-07-18

申请人： GENERAL INSTRUMENT CORPORATION OF DELAWARE

发明人： Paik, Woo H. ,  Lery, Scott A. ,  Tom, Adam S.

IPC分类号： H04L27/38 ,  H04L25/03

CPC分类号： H04L25/0314 ,  H04L27/3827

摘要： A method and apparatus are provided for adaptively equalizing data signals in a communications receiver. An unequalized data signal is demodulated. The demodulated data signal is filtered in an adaptive equalizer (60) that initially updates adaptive filter coefficients using error signals derived from a first algorithm. A carrier lock signal is generated (62, 78) when a phase error of a filtered signal output from the adaptive equalizer reaches a threshold value. The adaptive filter coefficients are updated (74) using error signals derived from a second algorithm instead of the first algorithm in response to the carrier lock signal (72). The first algorithm is a self-recovering equalization algorithm such as the Constant Modulus Algorithm. The second algorithm can be a decision directed algorithm. Carrier phase is recovered without the use of a phase rotator or phase de-rotator, by locating the adaptive equalizer inside of the carrier recovery loop (56). The invention is particularly adapted for use in the recovery of multilevel amplitude modulated data, such as QAM data.

摘要翻译： 提供了一种用于在通信接收机中自适应地均衡数据信号的方法和装置。 解调不平等的数据信号。 解调的数据信号在自适应均衡器（60）中被滤波，自适应均衡器（60）首先使用从第一算法导出的误差信号来更新自适应滤波器系数。 当从自适应均衡器输出的滤波信号的相位误差达到阈值时，产生载波锁定信号（62,78）。 使用从第二算法导出的误差信号，而不是响应于载波锁定信号（72）的第一算法来更新（74）自适应滤波器系数。 第一种算法是自恢复均衡算法，如恒模算法。 第二种算法可以是决策导向算法。 通过将自适应均衡器定位在载体恢复回路（56）内部，不使用相位旋转器或相位去旋转器来恢复载波相位。 本发明特别适用于恢复诸如QAM数据的多电平幅度调制数据。