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    METHODS AND APPARATUS FOR SMART MEMORY INTERFACE
    1.
    发明公开
    METHODS AND APPARATUS FOR SMART MEMORY INTERFACE 有权
    用于智能存储器接口的方法和设备

    公开(公告)号：EP3264415A1

    公开(公告)日：2018-01-03

    申请号：EP17171409.0

    申请日：2017-05-16

    申请人： Altera Corporation

    发明人： Teh, Chee Hak

    IPC分类号： G11C8/00 ,  G11C7/00 ,  G06F12/00 ,  G06F13/00 ,  G06F3/00 ,  G11C7/10 ,  G06F12/1072 ,  G06F13/16 ,  G11C8/16

    CPC分类号： G06F3/0664 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0632 ,  G06F3/0683 ,  G06F11/1068 ,  G06F13/1668 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/419 ,  G11C29/52

    摘要： One embodiment relates to a memory structure that includes a bank group and a port emulation circuit module. The bank group includes a plurality of memory banks, each memory bank having one read port and one write port. The port emulation circuit module provides a group read/write port and a group read port for the bank group. The port emulation circuit module includes a port emulation control circuit that receives control signals including a first address for a group read/write port and a second address for a group read port, a first data path circuit for the group read/write port, and a second data path circuit for the group read port, wherein the second data path circuit outputs a second read data. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种包括存储体组和端口仿真电路模块的存储器结构。 银行组包括多个存储体，每个存储体具有一个读端口和一个写端口。 端口仿真电路模块为该组群提供组读取/写入端口和组读取端口。 端口仿真电路模块包括端口仿真控制电路，该端口仿真控制电路接收包括用于组读取/写入端口的第一地址和用于组读取端口的第二地址，用于组读取/写入端口的第一数据路径电路的控制信号，以及 用于所述组读取端口的第二数据路径电路，其中所述第二数据路径电路输出第二读取数据。 其他实施例和特征也被公开。

    MEMORY SYSTEM WITH POINT-TO-POINT REQUEST INTERCONNECT
    2.
    发明授权
    MEMORY SYSTEM WITH POINT-TO-POINT REQUEST INTERCONNECT 有权
    与POINT-TO-POINT CONNECTION REQUEST存储系统

    公开(公告)号：EP2143107B1

    公开(公告)日：2017-03-22

    申请号：EP08742848.8

    申请日：2008-04-11

    申请人： Rambus Inc.

    发明人： PEREGO, Richard, E. ,  WARE, Frederick, A.

    IPC分类号： G11C5/06

    CPC分类号： G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

    摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

    INTERCONNECT SYSTEMS AND METHODS USING HYBRID MEMORY CUBE LINKS
    3.
    发明公开
    INTERCONNECT SYSTEMS AND METHODS USING HYBRID MEMORY CUBE LINKS 审中-公开
    VERBINDUNGSSYSTEME UND VERFAHREN MIT HYBRIDER MEMORY-CUBE-VERBINDUNGEN

    公开(公告)号：EP3140748A1

    公开(公告)日：2017-03-15

    申请号：EP15789012.0

    申请日：2015-05-01

    申请人： Micron Technology, Inc.

    发明人： LEIDEL, John D.

    IPC分类号： G06F13/16 ,  G06F12/00

    CPC分类号： G06F3/0607 ,  G06F3/0659 ,  G06F3/0685 ,  G06F13/1621 ,  G06F13/1657 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/40 ,  G06F13/4022 ,  G06F13/4234 ,  G06F2212/205 ,  G11C7/1075 ,  G11C21/00

    摘要： System on a Chip (SoC) devices include two packetized memory buses for conveying local memory packets and system interconnect packets. In an in-situ configuration of a data processing system two or more SoCs are coupled with one or more hybrid memory cubes (HMCs). The memory packets enable communication with local HMCs in a given SoC's memory domain. The system interconnect packets enable communication between SoCs and communication between memory domains. In a dedicated routing configuration each SoC in a system has its own memory domain to address local HMCs and a separate system interconnect domain to address HMC hubs, HMC memory devices, or other SoC devices connected in the system interconnect domain.

    摘要翻译： 片上系统（SoC）设备包括用于传送本地存储分组和系统互连分组的两个分组化存储器总线。 在数据处理系统的原位配置中，两个或更多个SoC与一个或多个混合存储立方体（HMC）耦合。 存储器分组使得能够与给定SoC的存储器域中的本地HMC进行通信。 系统互连分组使得SoC之间的通信和存储器域之间的通信成为可能。 在专用路由配置中，系统中的每个SoC都有自己的存储器域，以解决本地HMC和单独​​的系统互连域，以解决连接在系统互连域中的HMC集线器，HMC存储设备或其他SoC设备。

    SYSTEM AND METHOD FOR RESOLVING DRAM PAGE CONFLICTS BASED ON MEMORY ACCESS PATTERNS
    4.
    发明公开
    SYSTEM AND METHOD FOR RESOLVING DRAM PAGE CONFLICTS BASED ON MEMORY ACCESS PATTERNS 审中-公开
    基于记忆模式的系统和方法解决DRAM分页冲突的

    公开(公告)号：EP3092648A1

    公开(公告)日：2016-11-16

    申请号：EP15700945.7

    申请日：2015-01-09

    申请人： Qualcomm Incorporated

    发明人： MONDAL, Mriganka ,  LO, Haw-Jing

    IPC分类号： G11C11/4096 ,  G11C7/10

    CPC分类号： G06F3/0611 ,  G06F3/0655 ,  G06F3/0673 ,  G06F12/0607 ,  G06F13/1626 ,  G06F2212/652 ,  G11C7/1042 ,  G11C7/1072 ,  G11C7/1075 ,  G11C11/4096 ,  Y02D10/14

    摘要： Systems, methods, and computer programs are disclosed for managing access requests to a DRAM memory device. One embodiment includes receiving memory access pattern data for at least one of a plurality of memory clients prior to a corresponding memory transaction with a DRAM memory device. Next, it is determined, based on the received memory access pattern data, that a future transaction of a first of the plurality of memory clients may create a future page conflict with a current transaction of a second of the plurality of memory clients. The future page conflict is then resolved by interleaving access to an associated bank in the DRAM memory device by the first and second memory clients according to the received memory access pattern data.

    摘要翻译： 系统，方法和计算机程序是游离缺失盘管理访问请求的DRAM存储设备。 一个实施例包括与DRAM存储器装置中的对应存储器事务之前接收对存储器的客户端的多个至少一个存储器存取模式数据。 接下来，确定开采，根据接收到的存储器访问模式的数据，做了第一存储客户端的多个可以创建存储客户端的多个第二的当前事务未来的分页冲突的未来交易。 未来分页冲突，然后由第一和第二存储器客户gemäß接收到的存储器存取模式数据交织在DRAM存储设备在相关银行获得解决。

    PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS
    6.
    发明公开
    PRE-CHARGING BITLINES IN A STATIC RANDOM ACCESS MEMORY (SRAM) PRIOR TO DATA ACCESS FOR REDUCING LEAKAGE POWER, AND RELATED SYSTEMS AND METHODS 有权
    在数据访问之前静态随机存取存储器（SRAM）中的预充电二线以降低泄漏功率，以及相关的系统和方法

    公开(公告)号：EP2976770A1

    公开(公告)日：2016-01-27

    申请号：EP14727682.8

    申请日：2014-05-02

    申请人： Qualcomm Incorporated

    发明人： CHAI, Chiaming ,  GE, Shaoping ,  LILES, Stephen, Edward ,  GARG, Kunal

    IPC分类号： G11C11/412 ,  G11C11/413 ,  G11C7/12 ,  G11C7/10

    CPC分类号： G11C11/413 ,  G11C7/1042 ,  G11C7/1075 ,  G11C7/12 ,  G11C11/412 ,  G11C11/419

    摘要： Embodiments disclosed herein include methods and apparatuses for pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power. The memory access logic circuit receives a memory access request comprising a data entry address to be accessed in a first data access path of a SRAM data array of the SRAM. The SRAM also includes a pre-charge circuit provided in a second data access path outside the first data access path. The pre-charge circuit is configured to enable pre-charging of the SRAM data array as part of the memory access request to avoid pre-charging bitlines in the SRAM data array during idle periods to reduce leakage power. The pre-charge circuit can enable pre-charging of the SRAM data array prior to data access such that the pre-charge circuit does not add latency to the first data access path.

    摘要翻译： 这里公开的实施例包括用于在数据访问之前对静态随机存取存储器（SRAM）中的位线进行预充电以减少泄漏功率的方法和设备。 存储器访问逻辑电路接收包括要在SRAM的SRAM数据阵列的第一数据存取路径中存取的数据入口地址的存储器存取请求。 SRAM还包括设置在第一数据存取路径外的第二数据存取路径中的预充电电路。 预充电电路被配置为使能SRAM存储器访问请求的一部分的SRAM数据阵列的预充电，以避免在空闲期间预充电SRAM数据阵列中的位线以减少泄漏功率。 预充电电路可以在数据访问之前启用对SRAM数据阵列的预充电，使得预充电电路不向第一数据存取路径增加等待时间。

    Metastability prediction and avoidance in memory arbitration circuitry
    8.
    发明公开
    Metastability prediction and avoidance in memory arbitration circuitry 审中-公开
    Metastabilitätsvorhersageund -vermeidung在Speicherarbitrierungsschaltung

    公开(公告)号：EP2838089A2

    公开(公告)日：2015-02-18

    申请号：EP14178460.3

    申请日：2014-07-25

    申请人： Altera Corporation

    发明人： Lewis, David

    IPC分类号： G11C7/10 ,  G11C7/22

    CPC分类号： G06F1/08 ,  G11C7/1075 ,  G11C7/222

    摘要： An integrated circuit with hazard prediction and prevention circuitry is provided. The hazard prediction circuitry may predict a future hazard condition between two periodic signals, and the hazard prevention circuitry may selectively delay at least one of the two periodic signals to avoid the predicted hazard condition. Single-port memory cells may provide multiport memory functionality using an arbitration circuit that includes the hazard prediction and prevention circuitry and receives memory access requests from at least two request generators. The arbitration circuit may operate in synchronous mode and perform port selection based on a predetermined logic table. The arbitration circuit may also operate in asynchronous mode and execute a memory access request as soon as it is received by the arbitration circuit. Metastability caused by receiving memory access requests at the same time from at least two request generators may be avoided with the hazard prediction and prevention circuitry.

    摘要翻译： 提供了具有危险预测和预防电路的集成电路。 危险预测电路可以预测两个周期性信号之间的将来的危险状况，危害预防电路可选择性地延迟两个周期信号中的至少一个，以避免预测的危险状况。 单端口存储器单元可以使用包括危险预测和防止电路的仲裁电路来提供多端口存储器功能，并且从至少两个请求发生器接收存储器访问请求。 仲裁电路可以在同步模式下操作，并且基于预定的逻辑表执行端口选择。 仲裁电路还可以以异步模式操作，并且一旦它被仲裁电路接收就执行存储器访问请求。 可以通过危险预测和防止电路来避免从至少两个请求生成器同时接收存储器访问请求引起的可移植性。

    CONTENTION-FREE MEMORY ARRANGEMENT
    9.
    发明公开
    CONTENTION-FREE MEMORY ARRANGEMENT 有权
    无竞争存储器结构

    公开(公告)号：EP2788983A2

    公开(公告)日：2014-10-15

    申请号：EP12784372.0

    申请日：2012-09-28

    申请人： Xilinx, Inc.

    发明人： WU, Ephrem, C. ,  SAHARIA, Gyanesh

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1075 ,  G11C5/04 ,  G11C29/023 ,  G11C29/028

    摘要： A memory arrangement (200) includes a plurality of memory blocks (208), a first group of access ports (204), and a second group of access ports (206). Routing circuitry (209) couples each pair of the first and second groups of access ports to a respective one of the memory blocks. Each pair includes a first access port from the first group and a second access port from the second group. The first access port has write access to a first portion of the respective memory blocks but not to a second portion of the memory block, and has read access to the second portion but not to the first portion. The second access port has write access to the second portion but not to the first portion, and has read access to the first portion but not to the second portion.