Method and apparatus for communicating compressed digital video signals using multiple processors
    1.
    发明公开
    Method and apparatus for communicating compressed digital video signals using multiple processors 失效
    用于通过多个处理器的装置中的压缩的数字视频信号的传输方法和设备。

    公开(公告)号:EP0499088A2

    公开(公告)日:1992-08-19

    申请号:EP92101401.5

    申请日:1992-01-29

    IPC分类号: H04N7/137 H04N11/00

    摘要: Digital video signals are processed by a plurality of independently operating processors (42, 44, 46, 48) to provide data for transmission in a compressed, motion compensated form. A video image frame area (10) is divided into a set of subframes (12, 16, 20, 24). The set of subframes is systematically shifted such that the individual subframes progressively cycle across and wrap around the video image frame area. For each successive video frame, video image data bounded by each of the different subframes is independently compressed using motion estimation to reduce data redundancy among the successive frames. The motion estimation is limited for each subframe of a current video frame to areas of a previous video frame that were bounded by the same subframe in the previous frame. In an illustrated embodiment, the set of subframes (12, 16, 20, 24) is shifted once for each successive video frame, and each subframe includes a refresh region (14, 18, 22, 26) whereby the video image frame area (10) is progressively refreshed as the subframes are shifted thereacross. Receiver apparatus (60-82) for use in decoding the independently processed subframe data is also disclosed.

    摘要翻译: 数字视频信号由unabhängig操作处理器的多个(42,44,46,48)以压缩,运动补偿形式,以提供用于传输的数据处理。一种视频图像帧区域(10)被划分为一组子帧( 12,16,20,24)。 该组子帧的系统地移检测所做的个体子帧周期逐步跨越并围绕视频图象帧区包裹。 对于每个连续的视频帧,视频图像数据由每个不同的子帧的边界是unabhängig利用运动估计以降低连续帧之间的数据冗余压缩。 运动估计被限制对于当前视频帧的每个子帧中的先前视频帧的区域thatwere由前一帧相同的子帧边界。 在图示的实施方式中,该组子帧的(12,16,20,24)被用于每个连续视频帧移位一次,并且每个子帧包括刷新区域(14,18,22,26),由此视频图像帧区域( 10)作为子帧被移位跨过被渐进刷新的。 因此在处理unabhängig子帧数据进行解码使用的接收器装置(60-82)是圆盘游离缺失。

    Variable length code word decoder for use in digital communication systems
    4.
    发明公开
    Variable length code word decoder for use in digital communication systems 失效
    存储器中,用于在数字通信系统中用于解码可变长度字和解码器和方法

    公开(公告)号:EP0562419A2

    公开(公告)日:1993-09-29

    申请号:EP93104282.4

    申请日:1993-03-16

    IPC分类号: H04N7/133 H03M7/30 H03M7/42

    摘要: Apparatus (10) is provided for decoding variable length code words to recover transform coefficients, such as DCT transform coefficients provided by a high definition television encoder. A first category of the code words has a length of no more than n bits. A second category has a length of greater than n bits. A feedback ROM (22) is used to decode the code words. Code words from the first category are processed by directly addressing a lookup table (80) in the ROM (22). Code words from the second category are processed using multiple passes through the ROM (22), wherein a portion of the data output during a prior pass is fed back (90) to address the memory during a subsequent pass.

    摘要翻译: 装置(10)被设置用于解码可变长度码字以恢复的变换系数:如DCT变换由高清晰度电视编码器提供系数。 码字的第一类具有不超过n位的长度。 第二类具有大于n位的长度。 反馈ROM(22)用于将码字进行解码。 从第一类的码字是通过在ROM(22)直接寻址的查找表(80)进行处理。 从第二类代码字是通过ROM(22),使用多遍处理,现有右期间worin所述数据输出的一部分被反馈(90)到随后的通过期间寻址存储器。

    Double buffer scheme for variable length decoder
    5.
    发明公开
    Double buffer scheme for variable length decoder 失效
    双缓冲区方案的可变长度解码器

    公开(公告)号:EP0598346A2

    公开(公告)日:1994-05-25

    申请号:EP93118303.2

    申请日:1993-11-11

    摘要: A method and apparatus are provided for decoding variable length codewords carried in data blocks. A first buffer is loaded with a succession of data blocks. A second buffer is loaded with a first data block from the first buffer during a decoding cycle. The variable length codewords from the first data block in the second buffer are decoded to recover information. The process continues, with the second buffer being loaded with one data block at a time to successively decode new data blocks during successive decoding cycles.

    摘要翻译: 提供了用于解码数据块中携带的可变长度码字的方法和设备。 第一个缓冲区加载了一系列数据块。 在解码周期期间,第二缓冲器被加载来自第一缓冲器的第一数据块。 来自第二缓冲器中的第一数据块的可变长度码字被解码以恢复信息。 该过程继续,第二缓冲器一次加载一个数据块,以在连续的解码周期中连续地解码新的数据块。

    Statistical multiplexer for a multichannel image compression system
    6.
    发明公开
    Statistical multiplexer for a multichannel image compression system 失效
    Statistischer Multiplexerfürein Multikanal-Bildkomprimierungssystem。

    公开(公告)号:EP0550843A1

    公开(公告)日:1993-07-14

    申请号:EP92121030.8

    申请日:1992-12-10

    IPC分类号: H04N7/137 H04N7/13

    摘要: A multichannel image compression system uses a plurality of encoders (10, 12 ... 14) to compress image data. A coding level command is provided to each of the encoders to specify a level of quality to be provided by each encoder. Encoded image data, provided by the encoders in response to the coding level command, is multiplexed (26) into a combined signal for transmission. The coding level command is adjusted in response to an accumulated amount of data from the combined signal, to maintain the accumulated data within a throughput capability of a communication channel (48). Although the coding level command may specify a global coding level that is the same for all of the encoders, the encoders can derive local coding levels from the global coding level to provide different encoding qualities. Decoder apparatus (30-46) is provided to recover an image from the compressed image data.

    摘要翻译: 多通道图像压缩系统使用多个编码器(10,12〜14)来压缩图像数据。 为每个编码器提供编码电平命令,以指定由每个编码器提供的质量水平。 由编码器响应于编码电平命令提供的编码图像数据被多路复用(26)成为用于发送的组合信号。 响应于来自组合信号的累积的数据量来调整编码电平命令,以将累积的数据保持在通信信道(48)的吞吐量能力内。 虽然编码电平命令可以指定对于所有编码器相同的全局编码电平,编码器可以从全局编码级别导出本地编码电平,以提供不同的编码质量。 提供解码器装置(30-46)以从压缩图像数据中恢复图像。

    Method and apparatus for communicating compressed digital video signals using multiple processors
    7.
    发明公开
    Method and apparatus for communicating compressed digital video signals using multiple processors 失效
    使用多个处理器传播压缩数字视频信号的方法和装置

    公开(公告)号:EP0499088A3

    公开(公告)日:1993-05-19

    申请号:EP92101401.5

    申请日:1992-01-29

    IPC分类号: H04N7/137 H04N11/00

    摘要: Digital video signals are processed by a plurality of independently operating processors (42, 44, 46, 48) to provide data for transmission in a compressed, motion compensated form. A video image frame area (10) is divided into a set of subframes (12, 16, 20, 24). The set of subframes is systematically shifted such that the individual subframes progressively cycle across and wrap around the video image frame area. For each successive video frame, video image data bounded by each of the different subframes is independently compressed using motion estimation to reduce data redundancy among the successive frames. The motion estimation is limited for each subframe of a current video frame to areas of a previous video frame that were bounded by the same subframe in the previous frame. In an illustrated embodiment, the set of subframes (12, 16, 20, 24) is shifted once for each successive video frame, and each subframe includes a refresh region (14, 18, 22, 26) whereby the video image frame area (10) is progressively refreshed as the subframes are shifted thereacross. Receiver apparatus (60-82) for use in decoding the independently processed subframe data is also disclosed.

    Multiple serial access memory for use in feedback systems such as motion compensated television
    8.
    发明公开
    Multiple serial access memory for use in feedback systems such as motion compensated television 失效
    用于反馈系统中的多个串行存取存储器,例如运动补偿电视

    公开(公告)号:EP0543197A3

    公开(公告)日:1994-04-20

    申请号:EP92118660.7

    申请日:1992-10-31

    IPC分类号: G11C7/00 G11C11/409

    摘要: A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

    摘要翻译: 提供多个串行存取存储器。 动态随机存取存储器(30)被寻址以向其输入数据并从其输出数据。 响应于提供给它的地址信号(34,36,38),从阵列(50)输出数据行。 多个串行输出端口(44,46,48)耦合到阵列的输出端,用于选择性地锁存从阵列输出的不同行数据。 串行输出端口(44,46,48)被定时以从其输出锁存的数据。 在一个图示的实施例中,每个串行输出端口包含一个移位寄存器(62,64,66,... 68),其长度等于存储器阵列(30)的宽度。 移位寄存器响应于第一定时信号(42,52)以锁存来自阵列(30)的一行数据。 第二定时信号致动移位寄存器以移位一行锁存数据。 耦合到移位寄存器的串行访问选择器(70)从串行输出端口输出移位数据的选定部分。 该存储器作为运动补偿帧间图像编码/解码系统的帧存储器具有特殊应用。

    Multiple serial access memory for use in feedback systems such as motion compensated television
    9.
    发明公开
    Multiple serial access memory for use in feedback systems such as motion compensated television 失效
    在反馈系统中使用复式串行存储器,如bewegungskompensiertem电视下载。

    公开(公告)号:EP0543197A2

    公开(公告)日:1993-05-26

    申请号:EP92118660.7

    申请日:1992-10-31

    IPC分类号: G11C7/00 G11C11/409

    摘要: A multiple serial access memory is provided. A dynamic random access memory (30) is addressed to input data thereto and output data therefrom. Rows of data are output from the array (50) in response to address signals (34, 36, 38) provided thereto. A plurality of serial output ports (44, 46, 48) is coupled to the output of the array for selectively latching different rows of data output from the array. The serial output ports (44, 46, 48) are clocked to output the latched data therefrom. In an illustrated embodiment, each of the serial output ports contains a shift register (62, 64, 66, ... 68) having a length equal to the width of the memory array (30). The shift register is responsive to a first timing signal (42, 52) for latching a row of data from the array (30). A second timing signal actuates the shift register to shift a row of latched data. A serial access selector (70) coupled to the shift register outputs a selected portion of the shifted data from the serial output port. The memory has particular application as the frame store for a motion compensated interframe image coding/decoding system.

    摘要翻译: 本发明提供一种多串行存取存储器。 一种动态随机存取存储器(30)被从写给向其输入数据和输出数据在那里。 数据行是从在响应所述阵列(50),以解决信号(34,36,38)提供给它的输出。 的串行输出端口(44,46,48)的多个耦合到所述阵列的输出用于选择性地从阵列锁存数据输出的不同的行。 串行输出端口(44,46,48)从时钟到输出锁存的数据在那里。 在图示的实施例中,每个串行输出端口的包含具有等于所述存储器阵列(30)的宽度的长度的移位寄存器(62,64,66,... 68)。 移位寄存器响应于从所述阵列(30)闩锁的一行数据的第一定时信号(42,52)。 第二定时信号致动所述移位寄存器移位锁存一行数据。 耦合到所述移位寄存器的串行访问选择器(70)输出从串行输出端口的移位的数据的所选部分,所述存储器具有特别的应用为帧存储器,用于运动补偿的帧间图像编码/解码系统。