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公开(公告)号：EP0289088A1
公开(公告)日：1988-11-02
申请号：EP88200797.4
申请日：1988-04-26
IPC分类号： G11C19/28
摘要： In a one-electrode/bit SPS CCD memory, a capacity reduction can be obtained by phase shift of one or more clock voltages. For an n -phase system with N groups of n electrodes, the storage capacity can thus be reduced stepwise from at most N(n-1) bits to N(n-2) bits, etc. The stay time of the bits stored is reduced by a corresponding factor, as a result of which the clock frequency in the series registers need not be changed.
By this reduction, the memory is more particularly suitable for storing television pictures both in the 625 lines system and in the 525 lines system.摘要翻译： 在单电极/位SPS CCD存储器中，通过一个或多个时钟电压的相移可以获得容量减小。 对于具有N组n个电极的n相系统，存储容量因此可以从最多N（n-1）位逐步减小到N（n-2）位等。存储的位的停留时间是 减少了相应的因素，结果串联寄存器中的时钟频率不需要改变。 通过这种减少，存储器更特别适合于在625行系统和525行系统中存储电视图像。
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32.发明公开Apparatus for compressing and/or expanding time base 失效Vorrichtung zur Kompression und / oder Dehnung einer Zeitbasis。
公开(公告)号：EP0282279A2
公开(公告)日：1988-09-14
申请号：EP88302040.6
申请日：1988-03-09
申请人： SONY CORPORATION
CPC分类号： G11C19/285 , G11C27/04 , H04N5/14 , H04N9/79
摘要： An apparatus for compressing and/or expanding time base using a CCD (22) adapted such that an input signal supplied to the CCD (22) is obtained as a signal with its time base compressed or expanded on the output side of the CCD (22), a first two-phase transfer clock pulse signal made up of first and second pulse train signals (Pʹø1, Pʹø2) having a first period and arranged to be 180° out of phase with each other is used for driving the CCD thereby to write the input signal to the CCD and a second two-phase transfer clock pulse signal made up of third and fourth pulse train signals (Qʹø1, Qʹø2) having a second period and arranged to be 180° out of phase with each other is used for driving the CCD thereby to read from the CCD a signal which is produced from the input signal with its time base compressed or expanded, in which the pulse width of the first pulse train signal (Pʹø1) is made virtually equal to the pulse width of the third pulse train signal (Qʹø1) and the pulse width is selected to be smaller than a half of the smaller one of the first period and the second period.
摘要翻译： 一种用于使用CCD（22）压缩和/或扩展时基的装置，其适于使得提供给CCD（22）的输入信号被获得作为在CCD（22）的输出侧被压缩或扩展的时基的信号 ），由第一和第二脉冲序列信号（P'o1，P'o2）构成的第一两相传输时钟脉冲信号具有第一周期并被布置为彼此相差180°，用于驱动 CCD，从而将输入信号写入CCD，以及由具有第二周期的第三和第四脉冲串信号（Q'o1，Q'o2）组成的第二两相传输时钟脉冲信号，并且被布置为180° 相位彼此用于驱动CCD，从而从CCD读取由其时基压缩或扩展的输入信号产生的信号，其中第一脉冲串信号（P'o1）的脉冲宽度为 实际上等于第三脉冲串信号（Q'o1）的脉冲宽度和脉冲宽度 被选择为小于第一周期和第二周期中较小的一半的一半。
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公开(公告)号：EP0280097A2
公开(公告)日：1988-08-31
申请号：EP88101709.9
申请日：1988-02-05
CPC分类号： G11C27/04 , G11C19/285
摘要： A floating diffusion region and a drain region are formed separately from each other in a substrate. A reset electrode is arranged above an area located between the drain region and the floating diffusion region. A voltage step-up circuit having a reference voltage generator (40) receiving a power source voltage (VDD) for generating a reference voltage (VREF) and a step-up circuit (50) receiving a clock pulse (CP) for applying a voltage level of the clock pulse to the reference voltage applies a voltage (VGG) to the drain region. The gate of a conversion E type MOS transistor for converting and outputting the charge stored in the floating diffusion region to a signal having a voltage level proportional to the charge amount is connected to the floating diffusion region. The reference voltage generator (40) has D type MOS transistor (41) and E type MOS transistor (42) connected in cascade for producing the reference voltage of the value corresponding to the variation from a process center of the manufacturing process of this charge transfer device. The D type MOS transistor (41) has the same conductivity type and construction as the MOS transistor formed of the reset electrode, the floating diffusion region and the drain region. The E type MOS transistor (42) has the same conductivity type as the conversion E type MOS transistor.
摘要翻译： 浮动扩散区域和漏极区域在基板中彼此分开地形成。 复位电极布置在位于漏极区域和浮动扩散区域之间的区域的上方。 一种升压电路，具有接收用于产生参考电压（VREF）的电源电压（VDD）的基准电压发生器（40）和接收用于施加电压的时钟脉冲（CP）的升压电路（50） 将时钟脉冲的电平与参考电压施加到漏极区域的电压（VGG）。 用于将存储在浮动扩散区域中的电荷转换并输出到具有与电荷量成比例的电压电平的信号的转换E型MOS晶体管的栅极连接到浮动扩散区域。 参考电压发生器（40）具有串联连接的D型MOS晶体管（41）和E型MOS晶体管（42），用于产生与该电荷转移的制造过程的处理中心的变化相对应的值的参考电压 设备。 D型MOS晶体管（41）具有与由复位电极，浮动扩散区域和漏极区域形成的MOS晶体管相同的导电类型和结构。 E型MOS晶体管（42）具有与转换型E型MOS晶体管相同的导电类型。
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公开(公告)号：EP0157607A3
公开(公告)日：1988-01-20
申请号：EP85302197
申请日：1985-03-29
发明人： Walker, James Terrell , Larsen, Raymond Sverre , Shapiro, Stephen Loeb , Chae, Soo Ik , Freytag, Dietrich Reinhold , Breidenbach, Martin
IPC分类号： G11C27/02
CPC分类号： G11C27/04 , G11C27/026
摘要： A high speed data storage array is disclosed utilizing a cell design allowing high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates (Q1, Q2) between the signal input and a storage capacitor (20). The gates are controlled by a high speed row clock (12) and low speed column clock (28) the instantaneous analog value of the signal being sampled and stored by a cell on coincidence of the two clocks.
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35.发明公开
公开(公告)号：EP0222434A1
公开(公告)日：1987-05-20
申请号：EP86201802.5
申请日：1986-10-17
CPC分类号： H04N5/2173 , G11C27/04
摘要： In an integrated circuit of this type having a reset transistor (S1) for a capacitance (C1) succeeded by an active information charge transfer transistor (S2) for the capacitance (C1), a clock pulse signal (CP) at the common switching electrode (CE) results in opposite switching. It is found in practice that a noise pattern present at a reset pulse level in the circuit output signal (OT) may cause problems in the case of further signal processing operations in the device. To solve the problems a control method is used with a clock pulse signal (CP) which has at least three signal levels (a, b, c) whilst the reset transistor (S1) only is conducting consecutively, whereafter the two transistors (S1 and S2) are non-conducting and the information charge transfer transistor (S2) only is subsequently conducting. The result is that part of the problematic noise pattern is suppressed, so that further signal processing operations in the device, for example, via a known signal clamping circuit (S3, C2) and a known signal sample-and-hold circuit (S4, C3) can be performed in an acceptable manner.
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公开(公告)号：EP0129470A1
公开(公告)日：1984-12-27
申请号：EP84401205.4
申请日：1984-06-13
申请人： THOMSON-CSF
发明人： Portmann, Jacques , Arques, Marc
IPC分类号： H04N3/15
CPC分类号： G11C27/04 , H04N5/3692 , H04N5/37213
摘要： La présente invention concerne un dispositif photosensible à l'état solide pour la détection d'un rayonnement électromagnétique comportant N photosenseurs (1) connectés par l'intermédiaire d'une zone de transition (3) à un dispositif de lecture (4) du type à transfert de charge.
Conformément à l'invention, le dispositif de lecture est constitué par deux registres à décalage (9, 10) à transfert de charge à N/2 entrées parallèles et à une sortie série qui reçoivent simultanément les charges détectées par les photosenseurs et les transfèrent vers un étage de lecture unique (11) sous l'action de tensions de commande choisies de manière à lire alternativement chaque registre.
La présente invention s'applique à la détection dans l'infrarouge ou dans le visible.摘要翻译： 用于检测电磁辐射的固态感光装置包括通过过渡区连接到电荷耦合型读取装置的N个光电传感器。 读数器具有两个电荷耦合轴寄存器，具有N / 2并行输入和一个串联输出。 由光电传感器检测的电荷由两个寄存器同时接收，并在所选择的控制电压的作用下传送到单个读取级，以允许每个寄存器的备用读取。
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公开(公告)号：EP0099583A2
公开(公告)日：1984-02-01
申请号：EP83107162.6
申请日：1983-07-21
发明人： Iida, Tetsuya , Sakaue, Tasuo
IPC分类号： H03H15/02
摘要： A circuit for obtaining an output from a CCD type signal processing circuit should operate satisfactorily in a high frequency band covering, for instance, video signals. For this purpose, the floating gate electrode (7) of the CCD is connected to a first potential level (V GG ) through first and second capacitors (C c , C o ). The connecting point of the floating gate electrode (7) in the series circuit is connected to a second potential level (V T ) through a first control switch (Q 2 ) which is driven by a reset clock pulse (OR); and the connecting point of the first and second capacitors is connected to a third potential level (V o ) through a second control switch (Q 1 ) which is driven by a reset clock pulse (OR), so that the output is provided at the connecting point of the capacitors.
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39.发明公开APPARATUS FOR SAMPLING, FILTERING AND MULTIPLEXING DATA. 失效APPARAT ZUM BILDEN VON MOMENTWERTEN，FILTERN UNDBÜNDELNVON DATEN。
公开(公告)号：EP0028650A4
公开(公告)日：1981-09-21
申请号：EP80901204
申请日：1980-12-01
申请人： GEN ELECTRIC
CPC分类号： G11C27/04
摘要： The apparatus accepts n analog input signals, on an essentially continuous basis, at respective n input terminals each of which is connected to a "second" electrode of a respective one of n capacitors (26) of a semiconductor structure (20).The respective "first" capacitor electrode is connected to a respective region of semiconductor material which has a conductivity opposite to that of a substrate of the semiconductor structure (20), which structure further comprises an n-stage charge transfer shift register (21). A clocking wave form generator (56) introduces serially n packets of fixed charge-content (due to a fixed voltage source 55) for storage in the n shift register stages. This forms an initial first sequence of charge packets. A gating circuit (74) then enables simultaneous alteration of the n stored fixed charge-content packets, each one in accordance with its respective analog input signal. This forms an initial second sequence of charge packets, which is read out serially. The first and second sequences are formed repetitively in such manner that a new first sequence is formed while the thereto previous second sequence is concurrently read out.
摘要翻译： 该装置在基本上连续的基础上在各自的n个输入端子处接受n个模拟输入信号，每个输入端子连接到半导体结构（20）的n个电容器（26）中的相应一个的“第二”电极，相应的 “第一”电容器电极连接到半导体材料的相应区域，半导体材料的导电性与半导体结构（20）的衬底的导电性相反，该结构还包括n级电荷转移移位寄存器（21）。 时钟波形发生器（56）串行地引入n个固定电荷量（由于固定电压源55）的分组以存储在n个移位寄存器级中。 这形成了电荷包的初始第一序列。 选通电路（74）然后能够根据其各自的模拟输入信号同时改变n个存储的固定电荷内容包。 这形成了电荷包的初始第二序列，其被串行读出。 第一和第二序列以这样的方式重复形成，即形成新的第一序列，同时读出其前一个第二序列。
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40.发明公开VERFAHREN ZUR VERARBEITUNG MEHRERER GLEICHZEITIG AUFTRETENDER TRANSIENTER ANALOG-SIGNALE 失效方法用于处理多个同样的问题瞬态模拟信号。
公开(公告)号：EP0031329A1
公开(公告)日：1981-07-08
申请号：EP80901068.0
申请日：1980-06-18
发明人： ALTMANN, Jürgen
CPC分类号： G11C27/026 , G11C27/04
摘要： L'analyse precise de grandeurs de mesure transitoires arrivant simultanement, disponibles directement ou sous forme de signaux electriques necessitait jusqu'ici un tres grand deploiement de moyens. Afin de reduire l'importance des moyens necessaires, les signaux arrivant simultanement sont memorises sous forme analogique tout en conservant leur information de temps et d'amplitude, sont retardes d'un intervalle de temps donne mais different pour chaque signal et sont ensuite transmis sur une meme ligne de sortie. Ainsi, a l'entree d'un systeme de traitement de signal qui suit, les signaux primitivement simultanes apparaissent de maniere successive, mais sont inchanges et peuvent etre traites successivement.
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