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    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING
    1.
    发明授权
    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING 有权

    公开(公告)号：EP2198429B1

    公开(公告)日：2018-10-31

    申请号：EP08801788.4

    申请日：2008-09-02

    申请人： Paul Scherrer Institut PSI

    发明人： RITT, Stefan ,  DINAPOLI, Roberto

    IPC分类号： G11C27/02 ,  G11C27/04 ,  G11C19/18 ,  G06G7/26

    CPC分类号： G11C27/024 ,  G06G7/26 ,  G11C19/188 ,  G11C27/04

    摘要： The present invention represents a technique to reduce the readout time of switched capacitor array (SCA) circuitries. A possible implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register clocked at 33 MHz for external digitization. The write signal for the sampling cells is generated by a chain of inverters (domino principle) generated on the chip. The domino wave is running continuously until stopped by a trigger. A read shift register clocks the contents of the sampling cells either to a multiplexed or to individual outputs, where it can be digitized with an external ADC. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV (after offset calibration) makes this chip ideally suited for low power, high speed, high precision waveform digitizing. Fabricated on an advanced CMOS process in a radiation hard design, the present chip is available in a 64-lead low profile quad flat pack (LQFP) and a 64-pin quad flat non-leaded package (QFN).

    SHIFT REGISTER, DRIVER CIRCUIT AND DISPLAY DEVICE
    2.
    发明公开
    SHIFT REGISTER, DRIVER CIRCUIT AND DISPLAY DEVICE 有权
    SCHIEBEREGISTER，TREIBERSCHALTUNG UND ANZEIGEVORRICHTUNG

    公开(公告)号：EP2827335A4

    公开(公告)日：2015-04-22

    申请号：EP13760746

    申请日：2013-03-05

    申请人： SHARP KK

    发明人： HORIUCHI SATOSHI ,  TANAKA SHINYA ,  TAGAWA AKIRA ,  IWASE YASUAKI ,  MIZUNAGA TAKAYUKI ,  IWAMOTO AKIHISA

    IPC分类号： G11C19/28 ,  G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G11C19/00

    CPC分类号： G09G3/3677 ,  G09G3/3674 ,  G09G2310/0281 ,  G09G2310/0286 ,  G11C19/28 ,  G11C27/04

    摘要： A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive.

    摘要翻译： 移位寄存器被配置为使得第一和第二中间级中的每一个包括（i）提供有时钟信号的第一输入端，（ii）被提供有与提供给该时钟信号的时钟信号相位不同的时钟信号的第二输入端 第一输入端子，（iii）经由输出晶体管连接到第一输入端子的输出端子，以及（iv）连接到第二输入端子和输出晶体管的设置电路，用于设定控制电位的电位 输出晶体管的端子，第二中间级包括控制电路，其控制电路（i）连接到第二中间级的设置电路，（ii）提供控制信号，操作周期（i） 提供给初始阶段的移位启动信号被激活，并且（ii）在最后阶段的输出从激活变为失活的时刻结束，并且当提供给第一输入端的时钟信号 第二中间级的命令在操作周期开始之后被初始化，提供给第二中间级的第二输入端的时钟信号是无效的。

    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING
    3.
    发明公开
    FAST READOUT METHOD AND SWITCHED CAPACITOR ARRAY CIRCUITRY FOR WAVEFORM DIGITIZING 审中-公开
    SCHNELLES AUSLESUNGSVERFAHREN UND SCHALTKONDENSATOR-ARRAYSCHALTUNG ZUR WELLENFORM-DIGITALISIERUNG

    公开(公告)号：EP2198429A1

    公开(公告)日：2010-06-23

    申请号：EP08801788.4

    申请日：2008-09-02

    申请人： Paul Scherrer Institut PSI

    发明人： RITT, Stefan ,  DINAPOLI, Roberto

    IPC分类号： G11C27/02 ,  G11C27/04

    CPC分类号： G11C27/024 ,  G06G7/26 ,  G11C19/188 ,  G11C27/04

    摘要： The present invention represents a technique to reduce the readout time of switched capacitor array (SCA) circuitries. A possible implementation is a SCA chip capable of sampling 12 differential input channels at a sampling speed of 10 MSPS to 5 GSPS. The analog waveform can be stored in 1024 sampling cells per channel, and can be read out after sampling via a shift register clocked at 33 MHz for external digitization. The write signal for the sampling cells is generated by a chain of inverters (domino principle) generated on the chip. The domino wave is running continuously until stopped by a trigger. A read shift register clocks the contents of the sampling cells either to a multiplexed or to individual outputs, where it can be digitized with an external ADC. It is possible to read out only a part of the waveform for reducing the digitization time. The high channel density, high analog bandwidth of 450 MHz, and low noise of 0.35 mV (after offset calibration) makes this chip ideally suited for low power, high speed, high precision waveform digitizing. Fabricated on an advanced CMOS process in a radiation hard design, the present chip is available in a 64-lead low profile quad flat pack (LQFP) and a 64-pin quad flat non-leaded package (QFN).

    摘要翻译： 本发明表示减少开关电容器阵列（SCA）电路的读出时间的技术。 可能的实现是SCA芯片能够以10 MSPS至5 GSPS的采样速度对12个差分输入通道进行采样。 模拟波形可以存储在每个通道的1024个采样单元中，并且可以通过33 MHz时钟的移位寄存器采样后进行外部数字化读出。 采样单元的写入信号由芯片上产生的反相器链（domino principle）产生。 多米诺骨牌一直持续运行，直到被触发器停止。 读取移位寄存器将采样单元的内容或多路复用或单独输出进行计时，其中可以使用外部ADC进行数字化。 只能读出波形的一部分以减少数字化时间。 高通道密度，450 MHz高模拟带宽和0.35 mV的低噪声（偏移校准后）使该芯片非常适合低功耗，高速度，高精度波形数字化。 该芯片采用先进的CMOS工艺制造，采用辐射硬设计，采用64引脚低成形四边形扁平封装（LQFP）和64引脚四边形扁平非引线封装（QFN）。

    Switching circuit and charge transfer device using same
    7.
    发明公开
    Switching circuit and charge transfer device using same 失效
    使用相同的开关电路和电荷耦合器件

    公开(公告)号：EP0734026A3

    公开(公告)日：1999-03-17

    申请号：EP96104156.3

    申请日：1996-03-15

    申请人： SONY CORPORATION

    发明人： Maki, Yasuhito, c/o Sony Corporation

    IPC分类号： G11C27/04

    CPC分类号： G11C27/04

    摘要： A switching circuit comprising a means for holding a signal or a DC component thereof, and a switching transistor for driving the holding means, wherein another means is included for shaping the trailing edge to be more obtuse in the fall of a driving pulse applied to a gate of the switching transistor. There is also disclosed a charge transfer device comprising a charge transferrer for transferring a signal charge, a charge-voltage converter for converting the transferred signal charge into a proportional voltage, and a driver for supplying a reset pulse to the charge-voltage converter so as to reset the capacitance thereof to a predetermined potential, wherein another a means is incorporated in the driver for shaping the trailing edge to be more obtuse in the fall of the reset pulse. Since the trailing edge of the reset pulse at the time of turning off the reset is rendered more obtuse, it becomes possible to reduce the coupling portion of the output waveform where the potential of a floating diffusion or a floating gate is varied by the capacitive coupling which is derived from the parasitic capacitance between a reset drain and a reset gate.

    Verzögerungsschaltung
    8.
    发明公开
    Verzögerungsschaltung 失效
    延迟电路

    公开(公告)号：EP0725404A3

    公开(公告)日：1998-10-07

    申请号：EP96200159

    申请日：1996-01-23

    申请人： PHILIPS PATENTVERWALTUNG ,  PHILIPS ELECTRONICS NV

    发明人： STRUCK SOENKE

    IPC分类号： G11C27/04 ,  H03H11/26

    CPC分类号： G11C27/04

    摘要： Die Erfindung bezieht sich auf eine Verzögerungsschaltung mit wenigstens zwei Speicherzellen (3,4,5,6,8,9), welche je ein kapazitives Speicherelement (20,26,40,45), einen Schreibtransistor (22,28,42,47), mittels dessen eine zu verzögernde Information aus einer Schreibleitung (18) in das kapazitive Speicherelement (20,26,40,45) einschreibbar ist, und einen Lesetransistor (21,27,41,46) aufweisen, mittels dessen eine Information aus dem kapazitiven Speicherelement (20,26,40,45) auf eine Leseleitung (19) auslesbar ist, und mit einer mittels eines ersten Steuertaktes getakteten Steueranordnung, welcher eingangsseitig ein Steuersignal zugeführt wird und welche miteinander gekoppelte Steuerschaltungen (11,12,13,14,15,16) aufweist, von denen jeweils eine je einer Speicherzelle (3,4,5,6,8,9) zugeordnet ist, wobei mittels des Eingangssignals jeder Steuerschaltung (11,12,13,14,15,16) der Lesetransistor (21,27,41,46) der zugeordneten Speicherzelle (3,4,5,6,8,9) und mittels des Ausgangssignals jeder Steuerschaltung (11,12,13,14,15,16) der Schreibtransistor (22,28,42,47) der zugeordneten Speicherzelle ansteuerbar ist, wobei jede Steuerschaltung (11,12,13,14,15,16) ein erstes (43,48,24,30) und ein diesem nachgeschaltetes zweites (44,49,25,31) Steuerelement aufweist, diejenigen Steuerschaltungen (14) ein drittes, dem ersten Steuerelement (30) vorgeschaltetes Steuerelement (29) aufweisen, deren vorgeschaltete Steuerschaltung (11) örtlich entfernt angeordnet ist, daß den dritten Steuerelementen (29) eingangsseitig das Ausgangssignal des ersten Steuerelementes (24) der jeweils vorgeschalteten, räumlich entfernt angeordneten Steuerschaltung (11) zugeführt wird, und daß die ersten Steuerelemente (43,48,24,30) der Steuerschaltungen (11,12,13,14,15,16) von dem ersten Takt und die zweiten (44,49,25,31) und dritten (29) Steuerelemente der Steuerschaltungen (11,12,13,14,15,16) von einem zweiten Takt getaktet werden.