公开(公告)号：EP1102405A1

公开(公告)日：2001-05-23

申请号：EP99402897.5

申请日：1999-11-19

申请人： ALCATEL

发明人： Van Herzeele, Geert Eric Lina

IPC分类号： H03M3/02

CPC分类号： H03M3/356 ,  H03M3/43 ,  H03M3/456 ,  H03M3/486

摘要： A transducer interface arrangement including sensor means (SM) for measuring a parameter such as temperature, pressure, ..., an Analog-to-Digital Converter (ADCb) including a Sigma-Delta Modulator (SDMb), and a selectable resistor string (SRSa). The data input of the Sigma-Delta Modulator is connected to the series combination of a first switched-capacitor module (SC1, SC1b), a first differential amplifier (A1), a second switched-capacitor module (SC2) and a second differential amplifier (A2), followed by a comparator (CP). The modulator further comprises a third (SC3) and a fourth (SC4) switched-capacitor module to which a reference voltage is applied and which are respectively connected to the input of the first and the second amplifier. To reduce the chip area and power consumption while increasing the performance of the arrangement, an offset canceling pre-amplifier to the A/D converter is advantageously replaced by a fifth switched-capacitor module (SC5), to which an offset voltage is applied. The offset voltage is provided, together with the reference voltage, by the selectable resistor string (SRSa). In addition to the improved offset correction, the present transducer interface arrangement is also provided with simple gain setting means. To this end, gain setting modules consisting of one or more switchable capacitive branches coupled in parallel with existing capacitors in the first switched-capacitor module (SC1b). The more branches which are added, the higher the gain.

摘要翻译： 一种换能器接口装置，包括用于测量诸如温度，压力等的参数的传感器装置（SM），包括Σ-Δ调制器（SDMb）的模数转换器（ADCb）和可选择的电阻串 SRSA）。 Σ-Δ调制器的数据输入连接到第一开关电容器模块（SC1，SC1b），第一差分放大器（A1），第二开关电容器模块（SC2）和第二差分放大器 （A2），后跟比较器（CP）。 调制器还包括施加参考电压并分别连接到第一和第二放大器的输入的第三（SC3）和第四（SC4）开关电容器模块。 为了在增加布置性能的同时减小芯片面积和功耗，对A / D转换器的偏移消除前置放大器有利地被施加了偏移电压的第五开关电容器模块（SC5）所取代。 偏移电压与参考电压一起由可选择的电阻串（SRSa）提供。 除了改进的偏移校正之外，本换能器接口装置还具有简单的增益设定装置。 为此，由第一开关电容器模块（SC1b）中的现有电容并联耦合的一个或多个可切换电容分支组成的增益设置模块。 增加的分支越多，收益越高。

公开(公告)号：EP0709970A2

公开(公告)日：1996-05-01

申请号：EP95307498.6

申请日：1995-10-20

申请人： THE GENERAL ELECTRIC COMPANY, p.l.c.

发明人： Joyce, Timothy R. ,  Thurston, Andrew M.

IPC分类号： H03M3/02

CPC分类号： H04L25/063 ,  H03M3/356 ,  H03M3/43 ,  H03M3/454

摘要： An analogue to digital converter circuit arrangement comprising: an input (24) to receive an analogue signal, a first sampling means (9) operating at a first sampling frequency and operative to generate at an output (23) a digital signal; and a DC correction feedback path (10a) connected between the output (23) and the input (24). The DC correction feedback path comprising in order between the output (23) and input (24) means (25) for integrating said signal at the output (23), second sampling means (27) for sampling the integrated signal at a second sampling frequency which is a much lower frequency than said first sampling frequency, a digital to analogue converter (29) and means (31) for subtracting from the analogue signal received at the input (24) the analogue signal at the output of the digital to analogue converter.

摘要翻译： 一种模数转换器电路装置，包括：用于接收模拟信号的输入端（24）;以第一采样频率工作的第一采样装置（9），用于在输出端（23）产生数字信号; 以及连接在输出（23）和输入（24）之间的DC校正反馈路径（10a）。 DC输出校正反馈路径包括输出（23）和输入（24）之间的顺序，用于在输出端（23）上积分所述信号的装置（25），用于以第二采样频率对积分信号进行采样的第二采样装置 其是比所述第一采样频率低得多的频率，数模转换器（29）和用于从输入端（24）接收的模拟信号中减去数模转换器输出端的模拟信号的装置（31） 。

公开(公告)号：EP0312672A1

公开(公告)日：1989-04-26

申请号：EP87480015.4

申请日：1987-10-19

申请人： International Business Machines Corporation

发明人： Cukier, Maurice ,  Marciano, Frédérik ,  Michel, Patrick

IPC分类号： H03M1/60 ,  H04B14/06

CPC分类号： H04B14/062 ,  H03M3/356 ,  H03M3/50

摘要： Offset correction circuit in a digital-to-analog coder (10) comprising a delta coder (18) providing a serial bit string at a high frequency F in response to digital words supplied at a low frequency f, and an analog integrator (22) providing an analog output signal (24) which is an analog representation of the digital words. The offset correction circuit avoids an offset to be introduced in the analog output of the integrator (22) when a PLO correction is taken to slow down or to speed up the clock controlling the input of the digital words. Such a circuit can be implemented by a state generator which provides a corrected pulse in place of the sigma-delta data which lasts half the duration of the offset.

摘要翻译： 数字 - 模拟编码器（10）中的偏移校正电路包括：增量编码器（18），响应于以低频f提供的数字提供高频F的串行比特串;以及模拟积分器（22） 提供作为数字字的模拟表示的模拟输出信号（24）。 偏移校正电路避免当采取PLO校正来减慢或加速控制数字字输入的时钟时，在积分器（22）的模拟输出中引入偏移量。 这种电路可以由状态发生器来实现，该状态发生器提供校正的脉冲来代替持续偏移持续时间的一半的Σ-Δ数据。