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33 条记录 (耗时 0.011 秒)

    FRACTAL SEQUENCING SCHEMES FOR OFFSET CANCELLATION IN SAMPLED DATA ACQUISITION SYSTEMS
    3.
    发明公开
    FRACTAL SEQUENCING SCHEMES FOR OFFSET CANCELLATION IN SAMPLED DATA ACQUISITION SYSTEMS 有权
    分数测序法胶印消去中ABTASTDATENERFASSUNGSSYSTEMEN

    公开(公告)号：EP1668779A1

    公开(公告)日：2006-06-14

    申请号：EP05741872.5

    申请日：2005-04-29

    申请人： Microchip Technology Incorporated

    发明人： QUIQUEMPOIX, Vincent ,  DEVAL, Philippe

    IPC分类号： H03M3/00

    CPC分类号： H03M3/356 ,  H03M3/43 ,  H03M3/438

    摘要： The present invention is directed to the isolation and cancellation of the offset voltage component typically experienced at the input of sampled-data analog systems. In an exemplary embodiment, offset isolation and cancellation may be performed during normal operation of the sampling circuitry. In an exemplary embodiment, the present invention combines a front-end switching topology with one or more differential integrator stages and a logic algorithm implemented in the differential integrator stages. In operation, the circuitry preferably performs a number of samples for each stage, applies an inversion factor to the samples in accordance with the algorithm and integrates the samples to effect the cancellation of the offset voltage without substantially affecting the sampled input.

    2-PHASE SWITCHED CAPACITOR FLASH ADC
    4.
    发明公开
    2-PHASE SWITCHED CAPACITOR FLASH ADC 审中-公开
    FLASH-ADC MIT EINEM 2-PHASEN-GESCHALTETEN KONDENSATOR

    公开(公告)号：EP2962392A1

    公开(公告)日：2016-01-06

    申请号：EP14708423.0

    申请日：2014-02-20

    申请人： Microchip Technology Incorporated

    发明人： QUIQUEMPOIX, Vincent

    IPC分类号： H03K5/15

    CPC分类号： H03M3/34 ,  H03K5/15 ,  H03M1/00 ,  H03M1/12 ,  H03M1/804 ,  H03M3/30 ,  H03M3/322 ,  H03M3/356 ,  H03M3/422

    摘要： An input stage for a switched capacitor analog-to-digital converter has a differential voltage input receiving an input voltage, a differential reference voltage input receiving a chopped reference voltage, a common voltage connection, and a differential output. A pair of input capacitors is coupled between the differential voltage input and the differential output and a pair of reference capacitors is coupled between the differential reference voltage input. A switching unit is controlled by a first and second phase operable during the first phase to connect a first terminal of the input capacitors with the common voltage connection and couple the first terminal of the reference capacitors with the inverted differential voltage reference; and during a second phase to connect the first terminal of the input capacitors with the differential input voltage and couple the first terminal of the reference capacitors with the non-inverted differential voltage reference.

    摘要翻译： 用于开关电容器模拟 - 数字转换器的输入级具有接收输入电压的差分电压输入端，接收斩波参考电压的差分参考电压输入，公共电压连接和差分输出。 一对输入电容器耦合在差分电压输入和差分输出之间，一对参考电容耦合在差分参考电压输入端之间。 开关单元由在第一阶段期间可操作的第一和第二相位来控制，以将输入电容器的第一端与公共电压连接相连，并将参考电容器的第一端与反相的差分电压基准耦合; 并且在第二阶段期间，将输入电容器的第一端子与差分输入电压连接，并将参考电容器的第一端子与非反相差分电压基准耦合。

    CAPACITANCE-TO-DIGITAL INTERFACE CIRCUIT FOR DIFFERENTIAL PRESSURE SENSOR
    6.
    发明公开
    CAPACITANCE-TO-DIGITAL INTERFACE CIRCUIT FOR DIFFERENTIAL PRESSURE SENSOR 有权
    容量数字转换器接口电路用于差压传感器

    公开(公告)号：EP1994641A2

    公开(公告)日：2008-11-26

    申请号：EP07762743.8

    申请日：2007-01-26

    申请人： Fisher-Rosemount Systems, Inc.

    发明人： WANG, Rongtai

    IPC分类号： H03M3/00

    CPC分类号： G01L9/12 ,  H03M3/356 ,  H03M3/43 ,  H03M3/438

    摘要： A two phase, second order capacitance-to-digital (CD) modulator includes a first stage sigma-delta integrator that forms charge packets as a function of sensor capacitance during an auto-zero phase and integrates the packets during an integration phase to produce an output voltage. The first stage integrator holds its output voltage during the auto-zero phase, so that a second stage sigma-delta integrator can sample the first stage output voltage during the auto-zero phase and integrate the sampled voltage during the integration phase.

    MESSVERSTÄRKUNGSVORRICHTUNG UND -VERFAHREN
    9.
    发明公开
    MESSVERSTÄRKUNGSVORRICHTUNG UND -VERFAHREN 有权
    测量增益器和程序

    公开(公告)号：EP2087596A1

    公开(公告)日：2009-08-12

    申请号：EP07819284.6

    申请日：2007-10-24

    申请人： SARTORIUS AG

    发明人： FELDOTTE, Heinrich ,  KLAUER, Alfred

    IPC分类号： H03M1/52

    CPC分类号： H03M3/34 ,  H03M3/356 ,  H03M3/43 ,  H03M3/456

    摘要： The invention relates to measurement amplification methods and devices for detecting a monopolar input signal (UE) by integrating A/D conversion. Before being digitised, the input signal (UE) is inverted according the so-called Chopper principle and converted into a bipolar intermediate signal (UZ). The invention is characterised in that a reference voltage (Uref) used in A/D conversion undergoes polarity changes synchronised with the polarity changes of the intermediate signal (UZ). Offset and drift are totally eliminated by totalling an even number of individual measurements.

    OFFSET CANCELLATION FOR SAMPLED-DATA CIRCUITS
    10.
    发明公开
    OFFSET CANCELLATION FOR SAMPLED-DATA CIRCUITS 有权
    偏置衰减关于样本数据电路

    公开(公告)号：EP1999758A2

    公开(公告)日：2008-12-10

    申请号：EP07758608.9

    申请日：2007-03-15

    申请人： Cambridge Analog Technology, LLC

    发明人： LEE, Hae-Seung

    IPC分类号： G11C27/02 ,  H03K5/00 ,  H03K17/00

    CPC分类号： H03H19/004 ,  G11C7/06 ,  G11C27/026 ,  H03M1/0607 ,  H03M1/403 ,  H03M1/442 ,  H03M3/356

    摘要： A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.