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    MECHANISM TO PRECLUDE SHARED RAM-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR
    41.
    发明公开
    MECHANISM TO PRECLUDE SHARED RAM-DEPENDENT LOAD REPLAYS IN AN OUT-OF-ORDER PROCESSOR 审中-公开
    机制，撤除公共RAM依赖LAST REPRODUCTIONS在平凡的处理器

    公开(公告)号：EP3032403A2

    公开(公告)日：2016-06-15

    申请号：EP15196892.2

    申请日：2015-11-27

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： COL, Gerard ,  EDDY, Colin ,  HENRY, G. Glenn

    IPC分类号： G06F9/38

    CPC分类号： G06F9/30083 ,  G06F1/3296 ,  G06F9/3834

    摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a random access memory, configured to store microcode patches corresponding to the out-of-order processor which, upon initialization, accesses said random access memory to retrieve said microcode patches.

    摘要翻译： 包括第一和第二保留站的装置。 第一保留站分派负载微指令，并在总线保持指示如果负载微指令是针对操作数从比核的高速缓冲存储器等规定的资源获取指定负载微指令。 第二保留站被耦合到保持总线，并调度一个或多个年轻的微指令。其中也取决于负载微指令供执行的数个时钟周期之后的第一负载微指令的调度之后，并且如果它被指示上 保持总线做的负载微指令是指定的负载微指令，所述第二保留站被配置直到负载微指令已经检索操作数失速的一个或多个微较新的指令调度。 的非核心资源的多元化包括随机存取存储器，用于存储微码的补丁对应于乱序处理器，其在初始化时，访问所述随机存取存储器，检索所述微代码补丁。

    Electrostatic discharge protection circuit
    42.
    发明公开
    Electrostatic discharge protection circuit 审中-公开
    Schutzschaltungfürelektrostatische Entladungen

    公开(公告)号：EP2937901A1

    公开(公告)日：2015-10-28

    申请号：EP14193178.2

    申请日：2014-11-14

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： Lee, Yeong-Sheng

    IPC分类号： H01L27/02 ,  H02H9/04

    CPC分类号： H02H9/04 ,  H01L27/0285 ,  H02H9/046

    摘要： An electrostatic discharge (ESD) protection circuit includes a first n-type transistor, a discharge acceleration circuit and a discharge time circuit. The first n-type transistor has a first terminal coupled to a supply voltage, a second terminal coupled to a reference voltage, and a gate, wherein the first n-type transistor couples the supply voltage to the reference voltage during an ESD event at an I/O pad. The discharge acceleration circuit is coupled to the gate of the first n-type transistor to the I/O pad during the ESD event and coupled to the gate of the first n-type transistor to the reference voltage when there is no ESD event. The discharge time circuit, coupled to the discharge acceleration circuit and the supply voltage, controls a discharge time of the first n-type transistor of coupling the supply voltage to the reference voltage during the ESD event at the I/O pad.

    摘要翻译： 静电放电（ESD）保护电路包括第一n型晶体管，放电加速电路和放电时间电路。 第一n型晶体管具有耦合到电源电压的第一端子，耦合到参考电压的第二端子和栅极，其中第一n型晶体管在ESD事件期间将电源电压耦合到参考电压， I / O焊盘。 放电加速电路在ESD事件期间耦合到第一n型晶体管的栅极到I / O焊盘，并且当没有ESD事件时，将第一n型晶体管的栅极耦合到参考电压。 耦合到放电加速电路的放电时间电路和电源电压控制在I / O焊盘的ESD事件期间将电源电压耦合到参考电压的第一n型晶体管的放电时间。