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公开(公告)号：EP3267585A1
公开(公告)日：2018-01-10
申请号：EP16200684.5
申请日：2016-11-25
发明人： Lee, Yeong-Sheng
摘要： A phase detector includes a clock delay circuit, a data delay circuit, a control circuit, a D flip-flop, and a logic circuit. The clock delay circuit delays a clock signal so as to generate a delay clock signal. The data delay circuit delays a data signal so as to generate a delay data signal. The control circuit adjusts the delay time of the clock delay circuit and the delay time of the data delay circuit according to the clock signal and the delay clock signal. The D flip-flop generates a register signal according to the data signal and the clock signal. The logic circuit generates an up control signal and a down control signal according to the data signal, the delay data signal, and the register signal so as to control a charge pump of a CDR (Clock Data Recovery) circuit.
摘要翻译： 相位检测器包括时钟延迟电路，数据延迟电路，控制电路，D触发器和逻辑电路。 时钟延迟电路延迟时钟信号以产生延迟时钟信号。 数据延迟电路延迟数据信号以产生延迟数据信号。 控制电路根据时钟信号和延迟时钟信号调整时钟延迟电路的延迟时间和数据延迟电路的延迟时间。 D触发器根据数据信号和时钟信号产生寄存器信号。 逻辑电路根据数据信号，延迟数据信号和寄存器信号产生上升控制信号和下降控制信号，以控制CDR（时钟数据恢复）电路的电荷泵。
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4.发明公开
公开(公告)号：EP2937901A1
公开(公告)日：2015-10-28
申请号：EP14193178.2
申请日：2014-11-14
发明人： Lee, Yeong-Sheng
CPC分类号： H02H9/04 , H01L27/0285 , H02H9/046
摘要： An electrostatic discharge (ESD) protection circuit includes a first n-type transistor, a discharge acceleration circuit and a discharge time circuit. The first n-type transistor has a first terminal coupled to a supply voltage, a second terminal coupled to a reference voltage, and a gate, wherein the first n-type transistor couples the supply voltage to the reference voltage during an ESD event at an I/O pad. The discharge acceleration circuit is coupled to the gate of the first n-type transistor to the I/O pad during the ESD event and coupled to the gate of the first n-type transistor to the reference voltage when there is no ESD event. The discharge time circuit, coupled to the discharge acceleration circuit and the supply voltage, controls a discharge time of the first n-type transistor of coupling the supply voltage to the reference voltage during the ESD event at the I/O pad.
摘要翻译： 静电放电（ESD）保护电路包括第一n型晶体管，放电加速电路和放电时间电路。 第一n型晶体管具有耦合到电源电压的第一端子，耦合到参考电压的第二端子和栅极，其中第一n型晶体管在ESD事件期间将电源电压耦合到参考电压， I / O焊盘。 放电加速电路在ESD事件期间耦合到第一n型晶体管的栅极到I / O焊盘，并且当没有ESD事件时，将第一n型晶体管的栅极耦合到参考电压。 耦合到放电加速电路的放电时间电路和电源电压控制在I / O焊盘的ESD事件期间将电源电压耦合到参考电压的第一n型晶体管的放电时间。
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公开(公告)号：EP3267582A1
公开(公告)日：2018-01-10
申请号：EP16199007.2
申请日：2016-11-16
发明人： Lee, Yeong-Sheng
CPC分类号： H03K17/6872 , H03K5/135 , H03K5/151 , H03K5/1565
摘要： A single-ended-to-differential converter (200) for driving an LVDS (Low Voltage Differential Signaling) driving circuit (fig. 1: 140) includes a first converting circuit (210), a second converting circuit (220), and a controller (230). The first converting circuit converts an input signal (SIN) into a first output signal (SOUT1). The first converting circuit (210) has a tunable delay time. The second converting circuit (220) converts the input signal into a second output signal. The second converting circuit (220) has a fixed delay time. The controller (230) generates a first control signal (SC1) and a second control signal (SC2) according to the first output signal (SOUT1) and the second output signal (SOUT2), so as to adjust the tunable delay time of the first converting circuit (210).
摘要翻译： 用于驱动LVDS（低压差分信号）驱动电路（图1：140）的单端至差分转换器（200）包括第一转换电路（210），第二转换电路（220）和 控制器（230）。 第一转换电路将输入信号（SIN）转换为第一输出信号（SOUT1）。 第一转换电路（210）具有可调延迟时间。 第二转换电路（220）将输入信号转换为第二输出信号。 第二转换电路（220）具有固定的延迟时间。 控制器230根据第一输出信号SOUT1与第二输出信号SOUT2产生第一控制信号SC1与第二控制信号SC2，以调整第一输出信号SOUT1与第二输出信号SOUT2的可调延迟时间， 转换电路（210）。
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公开(公告)号：EP2958263B1
公开(公告)日：2018-08-08
申请号：EP14192781.4
申请日：2014-11-12
发明人： Lee, Yeong-Sheng
CPC分类号： H03K5/131 , H03K3/0375 , H03K2005/00058 , H03L7/0807 , H03L7/0814 , H04B1/16 , H04L7/0037 , H04L7/0337
摘要： A hold-time optimization circuit (100) includes a correction circuit (110) and a delay control circuit (170). The delay control circuit delays a clock signal (CLK) for a delay time (T) so as to generate a delay clock signal (CKLD). The correction circuit generates a correction pulse signal (CP) according to transition edges of a data signal (DA) and transition edges of the delay clock signal (CKLD). The delay time (T) of the delay control circuit (170) is optimized according to the correction pulse signal. The data signal is sampled according to the delay clock signal.
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7.发明公开Hold-time optimization circuit and receiver with the same 有权Haltezeitoptimierimungungsschaltung和Empfängerdamit
公开(公告)号：EP2958263A1
公开(公告)日：2015-12-23
申请号：EP14192781.4
申请日：2014-11-12
发明人： Lee, Yeong-Sheng
CPC分类号： H03K5/131 , H03K3/0375 , H03K2005/00058 , H03L7/0807 , H03L7/0814 , H04B1/16 , H04L7/0037 , H04L7/0337
摘要： A hold-time optimization circuit (100) includes a correction circuit (110) and a delay control circuit (170). The delay control circuit delays a clock signal (CLK) for a delay time (T) so as to generate a delay clock signal (CKLD). The correction circuit generates a correction pulse signal (CP) according to transition edges of a data signal (DA) and transition edges of the delay clock signal (CKLD). The delay time (T) of the delay control circuit (170) is optimized according to the correction pulse signal. The data signal is sampled according to the delay clock signal.
摘要翻译： 保持时间优化电路（100）包括校正电路（110）和延迟控制电路（170）。 延迟控制电路将时钟信号（CLK）延迟延迟时间（T），以产生延迟时钟信号（CKLD）。 校正电路根据数据信号（DA）的过渡沿和延迟时钟信号（CKLD）的过渡沿产生校正脉冲信号（CP）。 延迟控制电路（170）的延迟时间（T）根据校正脉冲信号被优化。 数据信号根据延迟时钟信号进行采样。
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