Method and apparatus for managing a database
    43.
    发明公开
    Method and apparatus for managing a database 失效
    用于管理数据库的方法和设备

    公开(公告)号:EP0100821A3

    公开(公告)日:1987-04-01

    申请号:EP83104483

    申请日:1983-05-06

    IPC分类号: G06F15/40

    CPC分类号: G06F9/463 G06F17/30

    摘要: A computing system is characterized by a database management system which provides method and apparatus for online definition of data descriptors (77) while maintaining the availability of data (76) and data descriptors not impacted by a concurrent definitional process. Under the control of the database management system (70) of the invention, the domain effected by the definitional process is determined, transactions which reference descriptors within the domain effected by the definitional process are marked for rebinding, prior-to-commit access by transactions which have not been prebound to objects within the domain effected by the definitional process is inhibited, and thereafter all accesses to objects in the domain are allowed.

    Interruption Method for a Data Processing System.
    44.
    发明公开
    Interruption Method for a Data Processing System. 失效
    Unterbrechungsmethodefürein Datenverarbeitungssystem。

    公开(公告)号:EP0206335A2

    公开(公告)日:1986-12-30

    申请号:EP86108686

    申请日:1986-06-25

    申请人: NEC CORP

    发明人: MATSUMOTO HAJIME

    IPC分类号: G06F9/42 G06F9/46 G06F9/48

    摘要: The invention relates to an interruption mechanism for a data processing system. The interruption mechanism comprises an execution processing unit (1) and a memory unit (2). The execution processing unit (1) includes a basic processor status storage (13), an extended processor status storage (14), current and new processor status block pointer storages (11, 12), and an interruption control section (17). Following the acceptance of interruption request, the interruption mechanism is sequentially operated by a plurality of steps. The interruption mechanism improves the performance of the execution processing unit (1).

    摘要翻译: 本发明涉及数据处理系统的中断机制。 中断机构包括执行处理单元(1)和存储单元(2)。 执行处理单元(1)包括基本处理器状态存储器(13),扩展处理器状态存储器(14),当前和新处理器状态块指针存储器(11,12)以及中断控制部件(17)。 在接受中断请求之后,通过多个步骤顺序地操作中断机制。 中断机制提高了执行处理单元(1)的性能。

    Method and apparatus for managing a buffer pool referenced by batch and interactive process
    45.
    发明公开
    Method and apparatus for managing a buffer pool referenced by batch and interactive process 失效
    用于管理与栈接入和交互式访问缓冲体系的方法和装置。

    公开(公告)号:EP0097256A2

    公开(公告)日:1984-01-04

    申请号:EP83105168.5

    申请日:1983-05-25

    IPC分类号: G06F12/00 G06F9/46

    摘要: Apparatus and method for managing a buffer pool (14) shared by sequential (16) and random processes (18). A data base manager includes a buffer manager (20) which: (1) maintains a normal least recently used (LRU) buffer chain and a sequential LRU buffer chain, the sequential LRU buffer chain being replicated on the normal LRU buffer chain; (2) places buffers released from a sequential process in both LRU buffer chains and buffers released from a random process only in the normal LRU buffer chain; and (3) responsive to a request for a buffer for a sequential process, steals the head buffer from the sequential LRU buffer chain, otherwise steals the head buffer from the normal LRU buffer chain. The buffer manager further includes means for conditionally asynchronously prefetching data set pages from the external storage device in response to a request for a data set page which is an integral multiple of a process defined prefetch quantity.

    摘要翻译: 装置和有条不紊用于管理由顺序的(16)共享缓冲池(14)和随机过程(18)。 其中A数据库管理器包括缓冲器管理器(20):(1)保持正常最近最少使用(LRU)链缓冲液和连续LRU缓冲器链,复制在正常LRU是缓冲器链顺序LRU缓冲器链; (2)放置在仅在正常LRU缓冲器链从一个随机过程中释放两种LRU缓冲器链和缓冲器顺序过程释放的缓冲液; 及(3)响应于用于为顺序过程的缓冲器的请求,窃取从时序LRU缓冲器链头部缓冲器,否则窃取从正常LRU缓冲器链头部缓冲器。 缓冲器管理器还包括用于从外部存储装置响应有条件异步地预取的数据集的页面用于数据集合页全部是上的过程中定义的预取量的内部的多个请求。

    Method and apparatus for restoring data in a computing system
    46.
    发明公开
    Method and apparatus for restoring data in a computing system 失效
    Verfahren undGerätzurDatarückgewinnungin einem Verarbeitungssystem。

    公开(公告)号:EP0097239A2

    公开(公告)日:1984-01-04

    申请号:EP83104485.4

    申请日:1983-05-06

    IPC分类号: G06F9/44 G06F9/46 G06F15/40

    摘要: Method and apparatus for assuring atomicity of user requested multi-row update operations to tables such as in a relation database (24), guaranteeing that for any update operation that succeeds all stated effects will have occurred and that for any update operation that fails the system state as perceived by the user remains unchaged. This is accomplished by establishing, in response to a multi-row update operation request, an execution module containing machine language code instructions implementing the update operation request with a savepoint request at the beginning of the execution module. For each set of instruction in or called by the execution module which modified the user perceived system state, undo information is logged to a soft log (20). Upon completing the execution module, the savepoint is dropped, causing all soft log information recorded since the savepoint to be deleted and releasing all resources held to guarantee restoration of the user perceived system state at the time of the savepoint request. Responsive to the detection of an error during execution of the module, the soft logged undo information is used to restore the user perceived state to that existing at the time of the savepoint request.

    摘要翻译: 用于确保用户所请求的多行更新操作对诸如关系数据库(24)中的表的原子性的方法和装置,保证对于所有已经发生的所有效果的任何更新操作都将发生,以及对于系统失败的任何更新操作 用户感知到的状态仍然被剥离。 这是通过响应于多行更新操作请求建立一个执行模块,该执行模块包含在执行模块的开始处使用保存点请求来实现更新操作请求的机器语言代码指令。 对于修改用户感知系统状态的执行模块中的每一组指令或调用,将撤消信息记录到软日志(20)。 完成执行模块后,保存点被删除,导致从保存点记录的所有软日志信息被删除,并释放所有保存的资源,以保证在保存点请求时恢复用户感知的系统状态。 响应于在模块执行期间检测到错误,软记录的撤消信息用于将用户感知状态恢复到保存点请求时存在的状态。

    A PROCESSOR ARCHITECTURE
    48.
    发明授权
    A PROCESSOR ARCHITECTURE 有权
    PROZESSORARCHITECTUR

    公开(公告)号:EP1208427B1

    公开(公告)日:2006-10-04

    申请号:EP00950169.3

    申请日:2000-07-14

    IPC分类号: G06F9/44 G06F12/02

    摘要: A processor architecture is adapted to program languages operating with a sequential instruction flow and handling data through use of lists or tuples or simple types. It comprises a program holding means (1), an instruction holding means (2, 3) a data memory means (5) storing data objects, and execution means (7). Means (4, 5, 6) are provided for handling references to data objects referenced by bindings and comprising means (6) to increment reference counts to a data object and to decrement reference counts to a data object in dependence of an actual instruction from the instruction holding means (2, 3).

    MICROPROCESSOR WITH REDUCED CONTEXT SWITCHING OVERHEAD AND CORRESPONDING METHOD
    50.
    发明授权
    MICROPROCESSOR WITH REDUCED CONTEXT SWITCHING OVERHEAD AND CORRESPONDING METHOD 有权
    具有减少上下文切换成本和程序微处理器

    公开(公告)号:EP1192538B1

    公开(公告)日:2004-03-31

    申请号:EP00922226.6

    申请日:2000-04-14

    IPC分类号: G06F9/46

    CPC分类号: G06F9/463 G06F9/3832

    摘要: A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.