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    MEMORY ARRAY
    41.
    发明公开
    MEMORY ARRAY 审中-公开
    存储器阵列

    公开(公告)号：EP1343171A4

    公开(公告)日：2004-04-21

    申请号：EP01270889

    申请日：2001-12-14

    申请人： SONY CORP

    发明人： KAIHATSU MINORU

    IPC分类号： G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/40 ,  G11C11/4099

    CPC分类号： G11C7/02 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2207/229

    摘要： A memory array for avoiding coupling noise in a cell plate voltage line. This memory array has first and second dummy word lines (DWL0, DWL1), first bit lines (BL), a first dummy memory cell (DMC0) connected between the first dummy word line (DWL0) and a common cell plate voltage line (VL), second bit lines (BLB), and a second dummy memory cell (DMC1) connected between the second dummy word line (DWL1) and a voltage line (Vl). When the first data is written into the first memory cell (MC0), the second dummy data with a polarity opposite to that of the first data is written into the second dummy memory cell (DMC1). When the second data is written into each of the second memory cell (MC), the first dummy data with a polarity opposite to that of the second data is written into each of the first dummy memory cell

    Signal transmission system using prd method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied
    42.
    发明公开
    Signal transmission system using prd method, receiver circuit for use in the signal transmission system, and semiconductor memory device to which the signal transmission system is applied 失效
    EMPFÄNGERSCHALTUNGFÜREINSIGNALÜBERTRAGUNGSSYSTEM

    公开(公告)号：EP1351249A2

    公开(公告)日：2003-10-08

    申请号：EP03013950.5

    申请日：1998-04-21

    申请人： FUJITSU LIMITED

    发明人： Saito, Miyoshi ,  Ogawa, Junji

    IPC分类号： G11C7/10 ,  H04L25/08 ,  H04L25/497

    CPC分类号： G11C7/1063 ,  G11C7/04 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/2227 ,  G11C2207/229 ,  H04L25/03878

    摘要： A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when switching the signal transmission line among the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched. This makes continuous readout possible and achieves an increase in the overall speed of the signal transmission system.

    摘要翻译： 通过消除由前面的数据引入的符号间干扰成分，构成信号传输系统，通过信号传输线路传输数据，而不需要为每一位预充电信号传输线。 信号传输线具有以分支结构或层次结构组织的多个可切换信号传输线，从多个信号传输线中的每一个连接至少一个读取数据的目标单元，以及读出电路，包括： 用于消除符号间干扰分量的电路连接到信号传输线，其中，符号间干扰成分消除电路减少在多个信号传输线之间切换信号传输线时引入的噪声，从而提供平滑的符号间干扰成分消除操作， 信号传输线被切换。 这使得连续读出成为可能，并且实现了信号传输系统的整体速度的增加。

    MEMORY ARRAY
    43.
    发明公开
    MEMORY ARRAY 审中-公开
    SPEICHERARRAY

    公开(公告)号：EP1343171A1

    公开(公告)日：2003-09-10

    申请号：EP01270889.7

    申请日：2001-12-14

    申请人： Sony Corporation

    发明人： KAIHATSU, Minoru

    IPC分类号： G11C11/40

    CPC分类号： G11C7/02 ,  G11C11/4076 ,  G11C11/4094 ,  G11C2207/229

    摘要： An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL) ; and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1).

    摘要翻译： 本发明的目的是获得能够防止在单元板电压线上产生耦合噪声的存储器阵列。 本发明的存储器阵列包括：第一和第二伪字线（DWL0和DWL1）; 连接到第一位线（BL），第一伪字线（DWL0）和公共单元板电压线（VL）的第一虚拟存储器单元（DMC0）; 以及连接到第二位线（BLB），第二虚拟字线（DWL1）和电压线（VL）的第二虚拟存储器单元（DMC1），其中与第一数据的极性相反极性的第二虚拟数据被写入 第二虚拟存储单元（DMC1），以便将第一数据写入第一存储单元（MC0），并将与第二数据的极性相反极性的第一虚拟数据写入第一虚拟存储单元（DMC0），以便 将第二数据写入第二存储单元（MC1）。

    Computer memory
    44.
    发明公开
    Computer memory 审中-公开
    Computerspeicher

    公开(公告)号：EP1326251A2

    公开(公告)日：2003-07-09

    申请号：EP02257780.3

    申请日：2002-11-11

    申请人： Hewlett-Packard Company

    发明人： Erlandson, Erik E. ,  Tremblay, David A.

    IPC分类号： G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/1021 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A memory (26) includes an address bus (ADDRESS), address counter (14), address decoder (38), comparator (18), and control circuit (24). During a data read or write cycle, the address bus (ADDRESS) receives an external address, the address counter (14) generates an internal address, which the address decoder (38) decodes, and the comparator (18) compares the external address to a value. Based on the relationship between the external address and the value, the comparator (18) enables or disables the data transfer. For example, such a memory (26) can terminate a page-mode read/write cycle by determining when the current external column address is no longer equal to the current internal column address. This allows the system to terminate the cycle after a predetermined number of data transfers by setting the external column address to a value that does not equal the internal column address. Alternatively, the comparator (18) can compare the external or internal address to a predetermined end address, and the memory (26) can terminate the cycle when the external or internal address equals the end address.

    摘要翻译： 存储器（26）包括地址总线（ADDRESS），地址计数器（14），地址解码器（38），比较器（18）和控制电路（24）。 在数据读或写周期期间，地址总线（ADDRESS）接收一个外部地址，地址计数器（14）产生地址解码器（38）进行解码的内部地址，比较器（18）将外部地址与 一个值。 基于外部地址和值之间的关系，比较器（18）启用或禁用数据传输。 例如，这样的存储器（26）可以通过确定当前外部列地址何时不再等于当前内部列地址来终止页模式读/写周期。 这允许系统通过将外部列地址设置为不等于内部列地址的值来在预定数量的数据传输之后终止循环。 或者，比较器（18）可以将外部或内部地址与预定的结束地址进行比较，并且当外部或内部地址等于结束地址时，存储器（26）可以终止循环。

    A high speed dram architecture with uniform access latency
    50.
    发明公开
    A high speed dram architecture with uniform access latency 有权
    Hochgeschwindigkeits-DRAM-Architektur mit einheitlicher Zugriffslatenz

    公开(公告)号：EP2276033A1

    公开(公告)日：2011-01-19

    申请号：EP10175918.1

    申请日：2001-06-29

    申请人： Mosaid Technologies Incorporated

    发明人： Demone, Paul

    IPC分类号： G11C7/22 ,  G11C11/4076

    CPC分类号： G11C7/22 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4076 ,  G11C2207/2281 ,  G11C2207/229

    摘要： A Dynamic Random Access Memory (DRAM) performs, read, write, and refresh operations. The DRAM includes a plurality of sub-arrays (504), each having a plurality of memory cells (604), each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device (911) for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit (908,910,912) is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse (WTPi). The read, write, and refresh operation are performed in the same amount of time.

    摘要翻译： 动态随机存取存储器（DRAM）执行，读取，写入和刷新操作。 DRAM包括多个子阵列（504），每个子阵列具有多个存储单元（604），每个存储单元与互补位线对和字线耦合。 DRAM还包括用于断言所选择的一条字线的字线使能装置（911）和用于断言所选位线对之一的列选择装置。 提供定时电路（908,910,912），用于响应于字线定时脉冲（WTPi）来控制字线使能装置，列选择装置以及读，写和刷新操作。 读取，写入和刷新操作在相同的时间量内执行。