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    IMPROVED CLOCK RECOVERY FOR DATA SIGNALS
    3.
    发明授权
    IMPROVED CLOCK RECOVERY FOR DATA SIGNALS 有权

    公开(公告)号：EP3089397B1

    公开(公告)日：2018-08-01

    申请号：EP16167681.2

    申请日：2016-04-29

    Applicant: Tektronix, Inc.

    Inventor： TAN, Kan

    IPC: H04L7/027 ,  H04L1/20 ,  H04L7/033 ,  G01R13/00 ,  H04L25/03

    CPC classification number: H04L7/033 ,  G01R13/00 ,  H04L1/20 ,  H04L1/205 ,  H04L7/0008 ,  H04L7/027 ,  H04L7/0331 ,  H04L25/03878

    Abstract: Embodiments of the present invention provide improved techniques for recovering clock information from data signals. In one embodiment, a general purpose device such as a real-time oscilloscope acquires a data signal. The device takes a derivative of the data signal, then computes the square or absolute of the derivative before applying a bandpass filter. The bandpass filter is a windowing function with a spectrum that is wider than the clock, and has a flat top and smooth transitions on both sides. In one embodiment, at Tukey window may be used. The device finds edge crossing times of the filtered result, and applies a phase-locked loop or lowpass filter to the edge crossing times in order to recover a stable clock signal. When the improved techniques are implemented in software, they may be used with any number of different equalizers that are required by various high-speed serial data link systems.

    BURST-TOLERANT DECISION FEEDBACK EQUALIZATION
    4.
    发明公开
    BURST-TOLERANT DECISION FEEDBACK EQUALIZATION 审中-公开

    公开(公告)号：EP3329593A1

    公开(公告)日：2018-06-06

    申请号：EP16831119.9

    申请日：2016-07-22

    Applicant: Rambus Inc.

    Inventor： GIOVANNINI, Thomas, J. ,  ABHYANKAR, Abhijit

    IPC: H03H7/30

    CPC classification number: H04L25/03057 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G11C19/00 ,  H04L25/03146 ,  H04L25/03878

    Abstract: A first sequence of data bits is shifted into storage elements of a signal receiver during a first sequence of bit-time intervals, and a memory access command indicates that a second sequence of data bits is to be received within the signal receiver during a second sequence of bit-time intervals. Contents of the shift-register storage elements are conditionally overwritten with a predetermined set of seed bits, depending on whether one or more bit-time intervals will transpire between the first and second sequences of bit-time intervals. Equalization signals generated based, at least in part, on contents of the shift-register storage elements are used to adjust respective signal levels representative of one or more bits of the second sequence of data bits.

    Asymmetric full duplex communication including device power communication
    8.
    发明公开
    Asymmetric full duplex communication including device power communication 有权
    与设备性能通信不对称全双工通信

    公开(公告)号：EP2247047A1

    公开(公告)日：2010-11-03

    申请号：EP09159216.2

    申请日：2009-04-30

    Applicant: EqcoLogic N.V.

    Inventor： Devuyst, Bram ,  Kuijk, Maarten

    IPC: H04L25/02

    CPC classification number: H04L5/1407 ,  H04B3/548 ,  H04L5/14 ,  H04L5/1423 ,  H04L5/1461 ,  H04L12/5602 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/0298 ,  H04L25/03878 ,  H04L47/10 ,  H04L47/22 ,  H04L47/30 ,  H04L47/35

    Abstract: An active transceiver circuit (212) for transmission of a low bitrate data signal (177) over and reception of a high bitrate data signal (166R) from a single ended transmission medium (105), the transmission medium (105) comprising an inner conductor (107) and a conductive shield layer (109), comprises:
    an input port (204) for receiving a low bitrate input data signal (101),
    an output port (202) for delivering a high bitrate output data signal (102),
    a differential input/output port (203) for launching a low bitrate data signal (177) into the single ended transmission medium (105) and for receiving a high bitrate data signal (166R) from the single ended transmission medium (105),
    a first and second single ended output driver (191, 192) adapted for each delivering, on their respective output nodes (111, 112), the low bitrate input data signal (101) shaped to a maximum slew rate that is at least 5 times smaller than the maximum slew rate of the received high bitrate data signal (166R), and
    a high bitrate receiver (117) for receiving the signals at output nodes (111, 112) of the first and second single ended output drivers (191, 192), and for generating a high bitrate output data signal (102) on the output port (202).
    The transceiver circuit (212) may be incorporated in a transceiver (200).

    SIGNAL RECEIVER APPARATUS AND WAVEFORM SHAPING METHOD
    10.
    发明公开
    SIGNAL RECEIVER APPARATUS AND WAVEFORM SHAPING METHOD 有权
    信号接收器装置和信号形状成型工艺

    公开(公告)号：EP2068518A1

    公开(公告)日：2009-06-10

    申请号：EP06798412.0

    申请日：2006-09-28

    Applicant: Fujitsu Microelectronics Limited

    Inventor： SHIMAMURA, Akira ,  MITA, Koichi ,  FUJISHIMA, Hideshi ,  ARAI, Takashi ,  KO, Shunichi ,  TERASAWA, Takuya ,  MIKAMI, Koji ,  KOMADA, Naoya

    IPC: H04L25/03

    CPC classification number: H04L25/03834 ,  H04L25/03878

    Abstract: To achieve an effective reflective waveform shaping in a bus system in which a plurality of transmitting ends and receiving ends are coupled, a device for monitoring a waveform state and calculating a waveform shaping parameter for each transmitting source, a device for storing the waveform shaping parameter calculated for each transmitting source, and a device for waveform shaping by the waveform shaping parameter are provided for the receiving end to perform waveform shaping. Therefore, a waveform can be shaped for each transmitting end coupled to a bus including a plurality of transmitting ends, and a reflective waveform can be corrected depending on a difference in the transmission direction which is not performed in the conventional waveform shaping in the bus coupling including a plurality of transmitting ends.

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