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    SYSTEM AND METHOD OF READING DATA FROM MEMORY CONCURRENTLY WITH SENDING WRITE DATA TO THE MEMORY
    3.
    发明公开
    SYSTEM AND METHOD OF READING DATA FROM MEMORY CONCURRENTLY WITH SENDING WRITE DATA TO THE MEMORY 有权
    系统和方法读取数据从内存中同时发送数据写入内存

    公开(公告)号：EP2973572A1

    公开(公告)日：2016-01-20

    申请号：EP14712517.3

    申请日：2014-03-06

    Applicant: SanDisk Technologies Inc.

    Inventor： PICHEN, Abdulla

    IPC: G11C7/10

    CPC classification number: G11C16/32 ,  G06F13/1626 ,  G11C7/1039 ,  G11C7/1042 ,  G11C16/10 ,  G11C16/26 ,  G11C2207/2209

    Abstract: A data storage device includes a memory, a controller, and a communication bus coupled to the memory and to the controller. The controller is configured to send a read-write command and write data to the memory via the communication bus. The read-write command indicates an address of requested data to be read from the memory. The controller is further configured to receive the requested data read from the memory. Communicating the requested data over the communication bus overlaps the write data being stored into the memory.

    Abstract translation: 一种数据存储装置包括存储器，控制器，以及耦合到所述存储器和所述控制器的通信总线。 所述控制器被配置为经由所述通信总线发送读写命令和写入数据到存储器。 读 - 写命令指示要被从存储器中读取所请求的数据的地址。 该控制器被进一步配置为接收从所述存储器中读出所请求的数据。 通过通信总线进行通信的请求的数据重叠的写数据被存储到存储器中。

    THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE
    4.
    发明公开
    THREE DIMENSIONAL MEMORY SYSTEM WITH COLUMN PIPELINE 有权
    与管道列选择三维存储器

    公开(公告)号：EP2681738A1

    公开(公告)日：2014-01-08

    申请号：EP12709997.6

    申请日：2012-02-15

    Applicant: SanDisk 3D LLC

    Inventor： YAN, Tianhong ,  BALAKRISHNAN, Gopinath ,  LEE, Jeffrey, Koon Yee ,  LIU, Tz-yi

    IPC: G11C7/10 ,  G11C7/18 ,  G11C13/00 ,  G11C17/16

    CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/18 ,  G11C8/08 ,  G11C8/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0069 ,  G11C17/16

    Abstract: A monolithic three dimensional array of non-volatile storage elements is arranged in blocks. The non-volatile storage elements are connected to bit lines and word lines. The bit lines for each block are grouped into columns of bit lines. The columns of bit lines include top columns of bit lines that are connected to selection circuits on a top side of a respective block and bottom columns of bit lines that are connected to selection circuits on a bottom side of the respective block. Programming of data is pipelined between two or more columns of bit lines in order to increase programming speed. One embodiment of the programming process includes selectively connecting two columns of bit lines to a set of one or more selection circuits, using the one or more selection circuits to selectively connect one of the two columns of bit lines to one or more signal sources, programming non-volatile storage elements for the column of bit lines that is currently connected to the one or more signal sources, and changing one of the columns of bit lines connected to the set of one or more selection circuits while another column of bit lines is being programmed.

    HIERARCHICAL ORGANIZATION OF LARGE MEMORY BLOCKS
    7.
    发明公开
    HIERARCHICAL ORGANIZATION OF LARGE MEMORY BLOCKS 有权
    分层组织GREAT内存块

    公开(公告)号：EP2529307A2

    公开(公告)日：2012-12-05

    申请号：EP11737561.8

    申请日：2011-01-26

    Applicant: Mosys, Inc.

    Inventor： ROY, Richard

    IPC: G06F12/00

    CPC classification number: G11C11/408 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1069 ,  G11C7/1096 ,  G11C11/4096 ,  G11C11/4097

    Abstract: A multi-bank memory system includes one or more levels of logical memory hierarchy to increase the available random cyclic transaction rate of the memory system. The memory system includes a plurality of multi-bank partitions, each having a corresponding partition interface. Each partition interface accesses the corresponding multi-bank partition at a first frequency. A global interface may access the partition interfaces at a second frequency, which is equal to the first frequency times the number of partition interfaces. Alternately, a plurality of cluster interfaces may access corresponding groups of the partition interfaces, wherein each cluster interface accesses the corresponding group of partition interfaces at a second frequency that is faster than the first frequency. A global interface accesses the cluster interfaces at a third frequency that is greater than the second frequency.

    Non-volatile memory control
    10.
    发明公开
    Non-volatile memory control 有权
    NichtflüchtigeSpeichersteuerung

    公开(公告)号：EP2275914A2

    公开(公告)日：2011-01-19

    申请号：EP10012010.4

    申请日：2002-09-27

    Applicant: LEXAR MEDIA, INC.

    Inventor： Gorobets, Sergey Anatolievich

    IPC: G06F3/06

    CPC classification number: G06F13/1615 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0688 ,  G06F13/4239 ,  G11C7/1039 ,  Y02D10/154

    Abstract: A method of operating a memory system having nonvolatile memory comprises implementing a pipelining sequence for transferring data to or from two or more memory arrays of the memory system; initiating an operation for access of the two or more memory arrays of the memory system; determining a number of active memory arrays of the memory system during the operation; introducing delay to the operation if the number of active memory arrays has reached an allowed limit; and continuing with the operation when the number of active memory arrays falls below the allowed limit.

    Abstract translation: 一种操作具有非易失性存储器的存储器系统的方法包括实现用于将数据传送到存储器系统的两个或多个存储器阵列或从存储器系统的两个或多个存储器阵 启动用于访问存储器系统的两个或更多个存储器阵列的操作; 在操作期间确定存储器系统的多个活动存储器阵列; 如果活动存储器阵列的数量达到允许的限制，则引入操作的延迟; 并且当活动存储器阵列的数量低于允许的极限时继续操作。

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