公开(公告)号：EP3977327A1

公开(公告)日：2022-04-06

申请号：EP20813090.6

申请日：2020-05-28

Applicant: Cylera, Inc.

Inventor： MACRAE, Calum ,  LOCASCIO, Jim ,  MASON, Karen ,  MASON, John ,  PHILPOTT, Richard ,  HUSSAIN, Muhammed Abid

IPC: G06F30/323 ,  G06F30/30 ,  G06F30/327 ,  G06F30/3308 ,  G06F30/39 ,  G06F30/367 ,  G06F30/398

公开(公告)号：EP3648104B1

公开(公告)日：2021-05-19

申请号：EP19208681.7

申请日：2014-01-07

Inventor： VILLEMOES, Lars

IPC: G10L19/093 ,  G06F30/327

公开(公告)号：EP3648104A1

公开(公告)日：2020-05-06

申请号：EP19208681.7

申请日：2014-01-07

Applicant: Dolby International AB

Inventor： VILLEMOES, Lars

IPC: G10L19/093 ,  G06F30/327

Abstract: The present document relates to audio source coding systems. In particular, the present document relates to audio source coding systems which make use of linear prediction in combination with a filterbank. A method for estimating a first sample (615) of a first subband signal in a first subband of an audio signal is described. The first subband signal of the audio signal is determined using an analysis filterbank (612) comprising a plurality of analysis filters which provide a plurality of subband signals in a plurality of subbands from the audio signal, respectively. The method comprises determining a model parameter (613) of a signal model; determining a prediction coefficient to be applied to a previous sample (614) of a first decoded subband signals derived from the first subband signal, based on the signal model, based on the model parameter (613) and based on the analysis filterbank (612); wherein a time slot of the previous sample (614) is prior to a time slot of the first sample (615); and determining an estimate of the first sample (615) by applying the prediction coefficient to the previous sample (614).

公开(公告)号：EP3912025B1

公开(公告)日：2024-05-29

申请号：EP20702950.5

申请日：2020-01-04

IPC: G06F8/41 ,  G06F30/32 ,  G06F30/327

CPC classification number: G06F8/41 ,  G06F8/4452 ,  G06F30/32 ,  G06F30/327

公开(公告)号：EP3893240B1

公开(公告)日：2024-04-24

申请号：EP21171483.7

申请日：2014-01-07

IPC: G10L19/093 ,  G06F30/327

CPC classification number: G10L19/093 ,  G06F30/327

公开(公告)号：EP4322044A1

公开(公告)日：2024-02-14

申请号：EP22836029.3

申请日：2022-08-04

Applicant: Changxin Memory Technologies, Inc.

Inventor： WU, Zengquan

IPC: G06F30/327 ,  G06F30/33

Abstract: The disclosure provides a method and an apparatus for checking a data processing circuit, and an electronic device. Performance check files of a plurality of timing sequence logic elements in the data processing circuit are acquired, and the data processing circuit is simulated based on the performance check files of the plurality of timing sequence logic elements, so as to obtain timing sequence information of the respective timing sequence logic elements. Therefore, the disclosure can check the timing sequence of the data processing circuit, which prevents the data processing circuit from failing to pass Command Bus Training (CBT), a relevant regulation check, etc. due to a great difference in timing sequence information, ensures that the data processing circuit can correctly process a signal, and improves the effectiveness of the data processing circuit during designing and using.

公开(公告)号：EP3346423B1

公开(公告)日：2023-12-20

申请号：EP17196986.8

申请日：2017-10-18

Inventor： DESOLI, Mr. Giuseppe ,  BOESCH, Mr. Thomas ,  CHAWLA, Mr. Nitin ,  SINGH, Mr. Surinder Pal ,  GUIDETTI, Mr. Elio ,  DE AMBROGGI, Mr. Fabio Giuseppe ,  MAJO, Mr. Tommaso ,  ZAMBOTTI, Mr. Paolo Sergio

IPC: G06N3/063 ,  G06N3/045 ,  G06N3/084 ,  G06F13/40 ,  G06N3/0464 ,  G06F30/327 ,  G06N3/044 ,  G06N3/047 ,  G06N7/01 ,  G06N20/10 ,  G06F115/08

公开(公告)号：EP4252137A1

公开(公告)日：2023-10-04

申请号：EP21820769.4

申请日：2021-11-11

Applicant: Raytheon Company

Inventor： REID, Stephen R. ,  DUTTA, Sandeep

IPC: G06F30/327 ,  G06F9/48 ,  G06F9/50 ,  G06F15/78 ,  G06F8/41

公开(公告)号：EP4170540A3

公开(公告)日：2023-08-09

申请号：EP22198617.7

申请日：2022-09-29

Applicant: Arteris, Inc.

Inventor： HIRECH, Mokhtar ,  de LESCURE, Benoît

IPC: G06F30/327 ,  G06F30/337 ,  G06F115/02 ,  G06F119/12 ,  G06F111/20

Abstract: A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.

公开(公告)号：EP4170540A2

公开(公告)日：2023-04-26

申请号：EP22198617.7

申请日：2022-09-29

Applicant: Arteris, Inc.

Inventor： HIRECH, Mokhtar ,  de LESCURE, Benoît

IPC: G06F30/327 ,  G06F30/337 ,  G06F115/02 ,  G06F119/12

Abstract: A system and method for implementing and generating a network-on-chip (NoC) topology based on area and timing assessment. A topology of the NoC is defined, approximations of area and timing of the topology without optimization are performed; and an exact, complete register transfer level (RTL) description of the topology is generated if the approximated area and timing satisfy constraints.