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51.发明公开TRANSMITTING DEVICE, RECEIVING DEVICE AND TRANSMITTING/RECEIVING SYSTEM 审中-公开SENDEVORRICHTUNG，EMPFANGSVORRICHUNG UND SENDE-EMPFANGSSYSTEM
公开(公告)号：EP2506433A4
公开(公告)日：2017-08-09
申请号：EP11814362
申请日：2011-06-02
发明人： AKITA HIRONOBU
CPC分类号： H04B1/0475 , H04B15/04 , H04B15/06 , H04L7/0008 , H04L7/0337
摘要： A transmitting device 10A has a transmission data generating part 11 and an output buffer part 12A. The transmission data generating part 11 transmits a data 1 and a clock 1, which are to be transmitted to a receiving device, and outputs them to the output buffer part 12A. The output buffer part 12A includes a data transmitting part 13 and a clock transmitting part 14A. The clock transmitting part 14A generates and transmits a clock intermittently phase-shifted. The data transmitting part 13 transmits the data in sync with the clock transmitted from the clock transmitting part 14A.
摘要翻译： 发送装置10A具有发送数据生成部11和输出缓冲部12A。 发送数据生成部11将要发送到接收装置的数据1和时钟1发送到输出缓冲部12A。 输出缓冲器部分12A包括数据发送部分13和时钟发送部分14A。 时钟发送部分14A产生并发送间歇相移的时钟。 数据发送部分13与从时钟发送部分14A发送的时钟同步地发送数据。
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52.发明公开TRANSMISSION DEVICE, RECEPTION DEVICE, TRANSMISSION/RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM 审中-公开ÜBERTRAGUNGSVORRICHTUNG，EMPFANGSVORRICHTUNG，ÜBERTRAGUNGS-UND EMPFANGSSYSTEM SOWIE BILDANZE系统
公开(公告)号：EP3054643A4
公开(公告)日：2017-06-07
申请号：EP14850150
申请日：2014-09-30
CPC分类号： G09G5/006 , G09G3/20 , G09G5/008 , G09G2352/00 , G09G2370/045 , G09G2370/08 , G09G2370/14
摘要： A mode switching notification in a first mode is transmitted from a transmission device 10 to a reception device 20 according to a first protocol. In a second mode, training data is transmitted from the transmission device 10 to the reception device 20, clock training is performed in the reception device 20, and a mode switching notification for the first mode is transmitted from the transmission device 10 to the reception device 20 according to a second protocol simpler and faster than the first protocol.
摘要翻译： 根据第一协议，第一模式下的模式切换通知从发送设备10发送到接收设备20。 在第二模式中，训练数据从发送设备10发送到接收设备20，在接收设备20中执行时钟训练，并且用于第一模式的模式切换通知从发送设备10发送到接收设备 20根据第二协议比第一协议更简单和更快。
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公开(公告)号：EP3131227A1
公开(公告)日：2017-02-15
申请号：EP15777544.6
申请日：2015-03-16
发明人： MIURA Satoshi
CPC分类号： H04L7/0331 , H03L7/0807 , H03L7/091 , H03L7/099 , H04L7/0054 , H04L7/0083 , H04L7/0087 , H04L7/033 , H04L7/048 , H04L7/10
摘要： Provided is a reception apparatus capable of shortening a time period until the original data and clock can be recovered from a digital signal after temporary superimposition of noise on the digital signal stops. A reception apparatus 20 includes a receiver unit 21, a voltage-controlled oscillator 22, a sampler unit 23, a control voltage generation unit 24, an error detection unit 25, a training control unit 26, and an equalizer control unit 27. The receiver unit 21 includes an equalizer unit 21 A. When the error detection unit 25 detects an error of a digital signal, the reception apparatus 20 causes a phase/frequency comparison by the control voltage generation unit 24 to be stopped.
摘要翻译： 本发明提供一种能够在数字信号的噪声暂时重叠停止之后缩短从数字信号恢复原始数据和时钟的时间的接收装置。 接收设备20包括接收器单元21，压控振荡器22，采样器单元23，控制电压生成单元24，错误检测单元25，训练控制单元26和均衡器控制单元27。 单元21包括均衡器单元21A。当错误检测单元25检测到数字信号的错误时，接收设备20使控制电压生成单元24的相位/频率比较停止。
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54.发明公开TRANSMISSION DEVICE, RECEPTION DEVICE, TRANSMISSION/RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM 审中-公开发送设备，接收设备，发送/接收系统和图像显示系统
公开(公告)号：EP3054639A1
公开(公告)日：2016-08-10
申请号：EP14850452.5
申请日：2014-09-30
CPC分类号： G09G3/3648 , G09G3/20 , G09G5/003 , G09G2310/08 , G09G2330/06 , G09G2370/08 , G09G2370/14
摘要： For serial data transmitted from a transmission device 10 to a reception device 20, a timing of transition from a first level to a second level is in each unit period. Image data serves as a first type of data for which two or more transitions from the second level to the first level are in each unit period. Control data serves as a second type of data for which one transition from the second level to the first level is in each unit period and the number of bits having the second level in each unit period corresponds to a control signal.
摘要翻译： 对于从发送设备10发送到接收设备20的串行数据，从第一电平到第二电平的转换定时在每个单位周期中。 图像数据用作第一种类型的数据，其中从第二级到第一级的两个或更多个转换处于每个单位周期中。 控制数据用作第二类型的数据，其中从第二级到第一级的一个转变处于每个单位时间段中，并且每个单位时间段中具有第二级的位数对应于控制信号。
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55.发明公开TRANSMITTER CIRCUIT, RECEIVER CIRCUIT, CLOCK EXTRACTING CIRCUIT, DATA TRANSMITTING METHOD, AND DATA TRANSMITTING SYSTEM 有权发送器电路，接收电路，时钟提取电路，数据传输方法和数据传输系统
公开(公告)号：EP1737174A4
公开(公告)日：2012-09-12
申请号：EP05730375
申请日：2005-04-12
发明人： OZAWA SEIICHI , OKAMURA JUN-ICHI , ISHIONE YOHEI , MIURA SATOSHI
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公开(公告)号：EP2211524B1
公开(公告)日：2012-07-11
申请号：EP09824721.6
申请日：2009-10-27
IPC分类号： H04L7/10
摘要： Provided are a transmitter apparatus, a receiver apparatus and a communication system wherein a simple structure is used to positively confirm a bit rate as changed. In a communication system (1), a transmitter apparatus (2) changes the bit rate of a serial data signal (S
data ) such that the bit rate of the serial data signal (S
data ) exhibits a fixed value for a period that is a fixed times of a clock cycle. The transmitter apparatus (2) then transmits the serial data signal (S
data ) to a receiver apparatus (3). In the receiver apparatus (3) having received the serial data signal (S
data ), it is determined whether the bit rate of the serial data signal (S
data ) exhibits the fixed value for the period that is a fixed times of the clock cycle. If so determined, the receiver apparatus (3) receives a training data (T
data ) from the transmitter apparatus (2) and then enters a process of confirming the bit rate as changed.摘要翻译： 提供了一种发送器设备，接收器设备和通信系统，其中使用简单的结构来肯定确认已改变的比特率。 在通信系统（1）中，发送装置（2）改变串行数据信号（S data）的比特率，使得串行数据信号（S data）的比特率在 一个时钟周期的固定时间。 发送器设备（2）然后将串行数据信号（S数据）发送到接收器设备（3）。 在接收到串行数据信号（S data）的接收器装置（3）中，确定串行数据信号（S data）的比特率是否在时钟周期的固定时间的周期内呈现固定值 。 如果这样确定，接收机设备（3）从发射机设备（2）接收训练数据（T data），然后进入确认比特率被改变的处理。
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57.发明公开DATA TRANSMITTING CIRCUIT AND DATA COMMUNICATION APPARATUS 有权DATENÜBERTRAGUNGSSCHALTKREISUND DATENKOMMUNIKATIONSVORRICHTUNG
公开(公告)号：EP2456151A1
公开(公告)日：2012-05-23
申请号：EP10811592.4
申请日：2010-06-17
发明人： YAMASAKI Daisuke
IPC分类号： H04L25/02
CPC分类号： H04L25/0284
摘要： Disclosed herein are a data transmission circuit and a data communication device that transmit data using an Alternating Current (AC)-coupled transmission line. The data transmission circuit includes a data transmission unit for transmitting data via a transmission line having a single AC-coupled line or a plurality of AC-coupled lines. When transmitting data, the data transmission unit transmits the data via the transmission line by sequentially setting a first electric potential corresponding to the data and a second electric potential different from the first electric potential. When transitioning from data transmission mode to an idle state, the data transmission unit sets an intermediate electric potential between the first electric potential and the second electric potential.
摘要翻译： 这里公开了一种使用交流（AC）耦合的传输线传输数据的数据传输电路和数据通信设备。 数据传输电路包括用于经由具有单个AC耦合线或多个AC耦合线的传输线发送数据的数据传输单元。 当发送数据时，数据发送单元通过依次设定与数据相对应的第一电位和与第一电位不同的第二电位，经由传输线发送数据。 当从数据传输模式转换到空闲状态时，数据传输单元设置第一电位和第二电位之间的中间电位。
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58.发明公开TRANSMISSION APPARATUS, RECEPTION APPARATUS, TRANSMISSION-RECEPTION SYSTEM, AND IMAGE DISPLAY SYSTEM 审中-公开SENDEGERÄT，EMPFANGSGERÄT，SENDE-EMPFANGSSYSTEM UND BILDANZEIGESYSTEM
公开(公告)号：EP2424153A1
公开(公告)日：2012-02-29
申请号：EP10767133.1
申请日：2010-04-22
发明人： OZAWA Seiichi , AKITA Hironobu
CPC分类号： H04L7/0008 , G09G3/3611 , G09G2310/08 , G09G2370/08 , H04L7/0091 , H04N5/12 , H04N5/66
摘要： The present invention provides a transmission apparatus and a reception apparatus easy to sample data correctly by a clock in the reception apparatus. In a detection section 25 of a reception apparatus 20 n , based on data output from a sampler section 23, both or either of detection of a phase difference between data received by a data reception section 21 and a clock received by a clock reception section 22, and/or waveform distortion of this data is performed. A detection signal indicating a result of detection by the detection section 25 is transmitted to a transmission apparatus 10 by a detection signal transmission section 26. In the transmission apparatus 10, by a control section 15, based on the detection signal received by a detection signal reception section 14, both or either of control of adjustment of a phase between data transmitted by a data transmission section 11 and a clock transmitted by a clock transmission section 12, and/or adjustment of an amplitude of the data is performed.
摘要翻译： 本发明提供一种易于通过接收装置中的时钟正确采样数据的发送装置和接收装置。 在接收装置20 n的检测部25中，根据从采样部23输出的数据，检测由数据接收部21接收到的数据与时钟接收部22接收的时钟之间的相位差 ，和/或该数据的波形失真。 表示检测部25的检测结果的检测信号由检测信号发送部26发送到发送装置10.在发送装置10中，通过控制部15，基于由检测信号 接收部14，执行由数据发送部11发送的数据与由时钟发送部12发送的时钟之间的相位的调整的控制和/或数据的振幅的调整。
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公开(公告)号：EP2421192A1
公开(公告)日：2012-02-22
申请号：EP10764421.3
申请日：2010-04-12
发明人： OZAWA Seiichi
IPC分类号： H04L7/02
CPC分类号： H04L7/0338
摘要： A reception apparatus is an apparatus for receiving serial data and includes a sampler portion, an edge detection portion, a logical addition operation portion, a timing determination portion, a register portion, a selector portion and a latch portion. The edge detection portion inputs data OSD[n] output from the sampler portion, performs an exclusive OR operation between the data OSD[n] and data OSD[n+1] which are adjacent to each other, and outputs data EDG[n] which is the result of the exclusive OR operation. The logical addition operation portion inputs the data EDG[n] output from the edge detection portion, performs, for a predetermined time period, an OR operation on the data EDG[n], with n o used as a reference value, with respect to each n which leaves a remainder of m when a difference (n - n o ) is divided by a value M, and outputs data EDGFLG[m] which is the result of the OR operation.
摘要翻译： 接收设备是用于接收串行数据的设备，并且包括采样器部分，边缘检测部分，逻辑加法操作部分，定时确定部分，寄存器部分，选择器部分和锁存部分。 边缘检测部分输入从采样器部分输出的数据OSD [n]，在彼此相邻的数据OSD [n]和数据OSD [n + 1]之间执行异或运算，并且输出数据EDG [n] 这是异或操作的结果。 逻辑加操作部分输入从边缘检测部分输出的数据EDG [n]，对于预定时间段，对数据EDG [n]进行OR运算，而不用作参考值 当差值（n-no）除以值M时剩下m的n，并输出作为OR运算结果的数据EDGFLG [m]。
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公开(公告)号：EP2211524A4
公开(公告)日：2011-06-08
申请号：EP09824721
申请日：2009-10-27
发明人： AKITA HIRONOBU , ISHIZONE YOHEI , OZAWA SEIICHI , MIURA SATOSHI
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