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公开(公告)号：EP0931315B1
公开(公告)日：2003-05-07
申请号：EP97911166.3
申请日：1997-10-01
发明人： GOLDMAN, Richard
IPC分类号： G11C17/18
摘要： To monitor the state of an antifuse capacitor, a transistor is connected to the capacitor such that it saturates only when the capacitor is not blown. Monitoring the base current of the transistor allows the state of the capacitor to be monitored without needing to use a conventional high-voltage comparator.
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公开(公告)号：EP1168366A1
公开(公告)日：2002-01-02
申请号：EP01401557.2
申请日：2001-06-14
发明人： Ferrant, Richard
摘要： Circuit claquable à sortie numérique comprenant un ensemble auto-stable de bascules 1, un ensemble de commande 2, en ensemble claquable 3, une porte logique 4 comprenant une première entrée reliée à un point commun 14 entre l'ensemble auto-stable 1 et l'ensemble claquable 3, et une deuxième entrée reliée à l'entrée de commande 20 du circuit, et un interrupteur 5 commandé par la sortie de la porte logique et disposé entre l'ensemble auto-stable 1 et une masse, et procédé associé.
摘要翻译： NAND门（4）具有连接到自动稳定的闩锁组件（1）和可吹塑组件（3）之间的公共点的输入。 第二输入连接到电子电路的控制输入。 断路器（5）由逻辑门的输出控制并且布置在自动稳定的组件和地之间。 独立权利要求包括：（1）读取可吹塑元件的过程
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53.发明公开Internal protection circuit and method for on chip programmable poly fuses 审中-公开Innere Schutzschaltung und Verfahrenfür片上programmierbare Sicherungen
公开(公告)号：EP1113452A2
公开(公告)日：2001-07-04
申请号：EP00311626.6
申请日：2000-12-22
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN 3 , MN 1 ) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (V main ). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MN main ) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.
摘要翻译： 具有至少一个可编程熔丝（F1）和ESD电路（MN3，MN1）的集成电路（10）防止当主电压电位（Vmain）上存在电压瞬变时熔丝（F1）被无意地烧断。 ESD电路优选地包括MOSFET开关，其由于电压瞬变而被耦合以比主熔丝编程开关（MNmain）更快地接通，从而确保主开关在电压瞬变期间保持关断以防止熔丝的无意吹风 F1。 该电路非常适合于可编程逻辑器件（PLD），允许低至6伏的读取电压，并允许高达40伏的编程电压。
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公开(公告)号：EP0727822B1
公开(公告)日：1999-08-11
申请号：EP96300693.7
申请日：1996-01-31
IPC分类号： H01L29/788 , H01L29/51 , H01L21/336 , H01L27/112 , G11C17/00
CPC分类号： H01L29/66825 , G11C17/14 , G11C17/18 , H01L27/115 , H01L29/51 , H01L29/685 , H01L29/788
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公开(公告)号：EP0644554A3
公开(公告)日：1998-03-18
申请号：EP94113467.8
申请日：1994-08-29
申请人： NEC CORPORATION
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： In a code setting circuit wherein pad terminals are supplied with a voltage pulse to burn out corresponding thin-film resistors, first transistors of first conductivity type are adapted to be turned on in response to a turn-on pulse and second transistors of the first conductivity type are provided. The channel of each second transistor is connected in parallel with the channel of each first transistor between a voltage source and one of circuit nodes at which desired potentials are developed and a digital setting signal is generated corresponding thereto. Inverters are connected between the nodes and the gate terminals of the second transistors to keep the nodes at the desired potentials. Third transistors of second conductivity type are provided to prevent the voltage source from being coupled through the second transistors to the pad terminals. Blocking means are provided respectively corresponding to the third transistors and the pad terminals. Each blocking means is connected between the other end of the channel of the corresponding third transistor and the corresponding pad terminal for preventing a noise pulse generated when the voltage pulse is applied to the corresponding pad terminal from being applied to the corresponding third transistor.
摘要翻译： 在代码设置电路中，其中焊盘端子被提供有电压脉冲以烧尽对应的薄膜电阻器，第一导电类型的第一晶体管适于响应于导通脉冲而导通，第一晶体管具有第一导电性 提供类型。 每个第二晶体管的通道与电压源和电路节点之间的每个第一晶体管的沟道并联连接，在所述电路节点之间产生所需的电位，并且相应地产生数字设定信号。 逆变器连接在节点和第二晶体管的栅极端子之间，以保持节点处于所需的电位。 提供第二导电类型的第三晶体管以防止电压源通过第二晶体管耦合到焊盘端子。 分别对应于第三晶体管和焊盘端子提供阻塞装置。 每个阻塞装置连接在对应的第三晶体管的通道的另一端和相应的焊盘端子之间，用于防止当施加到相应焊盘端子的电压脉冲施加到相应的第三晶体管时产生的噪声脉冲。
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公开(公告)号：EP0727822A2
公开(公告)日：1996-08-21
申请号：EP96300693.7
申请日：1996-01-31
IPC分类号： H01L29/788 , H01L29/51 , H01L21/336 , H01L27/112 , G11C17/00
CPC分类号： H01L29/66825 , G11C17/14 , G11C17/18 , H01L27/115 , H01L29/51 , H01L29/685 , H01L29/788
摘要： A memory apparatus has, on a substrate 1007, a first semiconductor region 1003 of one conduction type, second and third semiconductor regions of a conduction type opposite to the one conduction type in contact with the first semiconductor region, a first electrode 1002 provided through an insulating layer above a region for separating the second semiconductor region and the third semiconductor region, and a second electrode 1001 provided through an insulating layer 1004 above the first electrode 1002, wherein a resistance value between the first electrode 1002 and the second electrode 1001 is arranged to change from a high-resistance state into a low-resistance state, thereby realizing large capacitance, low cost, capability of writing, quick writing and reading, high reliability, low dissipation power, and so on.
摘要翻译： 存储装置在衬底1007上具有与一个导电类型相反的导电类型的一个导电类型的第一半导体区域，第二和第三半导体区域与第一半导体区域接触，第一电极1002通过 位于第二半导体区域和第三半导体区域分离区域上方的绝缘层以及穿过第一电极1002上方的绝缘层1004设置的第二电极1001，其中第一电极1002和第二电极1001之间的电阻值被布置 从高电阻状态转变为低电阻状态，从而实现了大容量，低成本，写入能力，快速写入和读取，高可靠性，低耗散功率等等。
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公开(公告)号：EP0466482B1
公开(公告)日：1996-06-12
申请号：EP91306270.9
申请日：1991-07-10
申请人： NEC CORPORATION
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G01R31/31702
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公开(公告)号：EP0652566A1
公开(公告)日：1995-05-10
申请号：EP94115745.5
申请日：1994-10-06
发明人： Canada, Miles Gaylord , Nicewicz, Michael , Rawlins, John Raymond , Rivadeneira, Carlos Gustavo
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse lactch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.
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公开(公告)号：EP0574131A3
公开(公告)日：1995-01-18
申请号：EP93303534.7
申请日：1993-05-07
申请人： ACTEL CORPORATION
发明人： Bakker, Gregory W.
IPC分类号： G11C17/18
CPC分类号： G11C17/18
摘要： A method for programming an antifuse of a selected technology type comprises the steps of (12) applying a preselected number of programming pulses to the antifuse at a voltage less than the maximum voltage at which antifuses of that selected technology type are known to program, (14) testing to see if the antifuse has been programmed, (20) increasing the programming voltage by a preselected increment and applying the preselected number of programming pulses to the antifuse if the antifuse has not been programmed, and repeating steps (12) to (20) until the antifuse has been programmed. The antifuse may be identified as defective if it does not program after a selected number of attempts.
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