公开(公告)号：EP4435786A1

公开(公告)日：2024-09-25

申请号：EP24164499.6

申请日：2024-03-19

申请人： NXP USA, Inc.

发明人： Roy, Anirban ,  Mahatme, Nihaar N. ,  Choy, Jon Scott

IPC分类号： G11C11/16 ,  G11C17/16 ,  G11C17/18 ,  G11C7/10 ,  G11C7/16

CPC分类号： G11C11/1675 ,  G11C17/18 ,  G11C7/1078 ,  G11C11/161 ,  G11C11/1677 ,  G11C11/1697 ,  G11C7/16 ,  G11C17/16

摘要： A magnetoresistive random access memory (MRAM) array includes MRAM cells, each MRAM cell having a corresponding Magnetic Tunnel Junction (MTJ) capable of being in a blown state or non-blown state, in which the blown state corresponds to a permanent breakdown of a tunnel dielectric layer of the corresponding MTJ. Write circuitry performs a one-time-programmable (OTP) write operation to blow selected MRAM cells. For each MRAM cell being blown, the write circuitry uses an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation. After detection of the onset, the write circuitry updates the initial OTP program reference, applies at least one additional OTP write pulse to the MRAM cell being blown, and uses the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.

公开(公告)号：EP3133609B1

公开(公告)日：2018-08-08

申请号：EP16183389.2

申请日：2016-08-09

申请人： eMemory Technology Inc.

发明人： WONG, Wei-Zhe ,  YANG, Ching-Sung ,  HSU, Ching-Hsiang

IPC分类号： G11C17/16 ,  G11C7/24

CPC分类号： G11C17/18 ,  G06F21/44 ,  G11C7/24 ,  G11C17/16

摘要： The invention provides a code generating apparatus and an OTP memory block. The code generating apparatus of present disclosure includes a plurality of first one time programming (OTP) memory cells, a reference signal provider and a sense amplifier. The first OTP memory cells are coupled to a first bit line. The reference signal provider provides a reference signal. Wherein, at least one of the first OTP memory cells provides a read current to the first bit line, and the sense amplifier compares the read current and the reference signal to generate an output code. A current value of the reference signal is set within a range, and the range is set by the bit current corresponding to a maximum bit count, such as that the output code is determined by a manufacturing variation of the at least one first OTP memory cell.

公开(公告)号：EP3345187A1

公开(公告)日：2018-07-11

申请号：EP16842708.6

申请日：2016-08-26

申请人： Lattice Semiconductor Corporation

发明人： OMID-ZOHOOR, Farrokh Kia ,  BUI, Nguyen, Duc ,  LY, Binh

IPC分类号： G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L27/11582 ,  H01L28/00

摘要： A non-volatile programmable bitcell has a read enable device with a source coupled with a bitline, an anti-fuse device with a gate coupled with a first write line, a drain coupled with a supply voltage and a source coupled with a drain of the read enable device. The bitcell has a fuse device coupled between a second write line and the drain of the read enable device. A magnitude of current flowing in the bitline, when the read enable device is enabled for reading, is dependent both on (1) a voltage level applied to the first write line and anti-fuse device state and on (2) a voltage level applied to the second write line and fuse device state. Usages include in a memory array, such as for FPGA configuration memory. The bitcell can be used as a multi-time programmable element, or to store multiple bit values.

公开(公告)号：EP3129987A4

公开(公告)日：2018-04-25

申请号：EP15777541

申请日：2015-02-11

申请人： MICRON TECHNOLOGY INC

发明人： WILSON ALAN J ,  WRIGHT JEFFREY

IPC分类号： G11C29/00 ,  G11C7/24 ,  G11C29/44

CPC分类号： G11C29/76 ,  G11C7/24 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/418 ,  G11C17/16 ,  G11C17/18 ,  G11C29/04 ,  G11C29/70 ,  G11C29/789 ,  G11C29/806 ,  G11C29/838 ,  G11C2029/4402

摘要： Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

公开(公告)号：EP2989636A4

公开(公告)日：2018-03-14

申请号：EP14891593

申请日：2014-12-12

申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD

发明人： GLENN HENRY G ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC分类号： G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC分类号： G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

摘要： An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

公开(公告)号：EP2989553A4

公开(公告)日：2018-03-14

申请号：EP14891596

申请日：2014-12-12

申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD

发明人： HENRY G GLENN ,  JAIN DINESH K ,  GASKINS STEPHAN

IPC分类号： G06F9/44 ,  G06F15/177 ,  G11C29/02 ,  H01L27/02

CPC分类号： G06F12/0893 ,  G06F1/3275 ,  G06F8/66 ,  G06F9/4403 ,  G06F12/0811 ,  G06F12/12 ,  G06F15/177 ,  G06F2212/222 ,  G06F2212/283 ,  G06F2212/601 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C2029/4402

摘要： An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

公开(公告)号：EP3276628A1

公开(公告)日：2018-01-31

申请号：EP17182842.9

申请日：2017-07-24

申请人： NXP USA, Inc.

发明人： Yang, Jianan

IPC分类号： G11C7/14 ,  G11C7/12 ,  G11C17/12 ,  G11C17/14 ,  G11C17/18

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C17/12 ,  G11C17/14 ,  G11C17/18

摘要： Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.

摘要翻译： 公开了用于操作只读存储器（ROM）的设备和方法。 用于操作ROM的方法包括利用耦合到虚拟位线的虚拟感测放大器来感测虚拟位线以产生保持器调整信号。 基于保持器调整信号，调整耦合到读出放大器电路的保持器电路的保持器强度。 读出放大器电路能够读出存储在ROM中的数据。

公开(公告)号：EP3214649A1

公开(公告)日：2017-09-06

申请号：EP15855744.7

申请日：2015-10-09

申请人： Floadia Corporation

发明人： TANIGUCHI Yasuhiro ,  KASAI Hideo ,  KAWASHIMA Yasuhiko ,  SAKURAI Ryotaro ,  SHINAGAWA Yutaka ,  OKUYAMA Kosuke

IPC分类号： H01L27/10 ,  G11C16/02 ,  G11C16/06 ,  G11C17/06

CPC分类号： H01L27/11206 ,  G11C17/06 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/10805 ,  H01L27/11502 ,  H01L27/11585

摘要： In an anti-fuse memory (2b) includes a rectifier element (3) of a semiconductor junction structure in which a voltage applied from a memory gate electrode (G) to a word line (WL1) is applied as a reverse bias in accordance with voltage values of the memory gate electrode (G) and the word line (WL1), and does not use a conventional control circuit. Hence, the rectifier element (3) blocks application of a voltage from the memory gate electrode (G) to the word line (WL1). Therefore a conventional switch transistor that selectively applies a voltage to a memory capacitor and a conventional switch control circuit allowing the switch transistor to turn on or off are not necessary. Miniaturization of the anti-fuse memory and a semiconductor memory device are achieved correspondingly.

摘要翻译： 在反熔丝存储器（2b）中包括半导体结结构的整流器元件（3），其中从存储器栅极电极（G）施加到字线（WL1）的电压作为反向偏置施加， 存储栅电极（G）和字线（WL1）的电压值，并且不使用传统的控制电路。 因此，整流器元件（3）阻止从存储器栅极电极（G）向字线（WL1）施加电压。 因此，不需要将电压选择性地施加到存储电容器的常规开关晶体管和允许开关晶体管导通或截止的常规开关控制电路。 反熔丝存储器和半导体存储器件的小型化相应地实现。

公开(公告)号：EP3057101B1

公开(公告)日：2017-08-30

申请号：EP16152107.5

申请日：2016-01-20

申请人： Toyota Jidosha Kabushiki Kaisha

发明人： SHIZUKA, Satoshi

IPC分类号： G06F12/02 ,  G06F9/445 ,  G11C17/18 ,  G11C16/10

CPC分类号： G06F12/0246 ,  G06F8/654 ,  G06F2212/7209 ,  G11C16/105 ,  G11C17/18

摘要： A first process part controls, based on data of a FLASH status 0 area included in a first block of a flash ROM, a rewriting process including erasing, writing and verifying on blocks of the flash ROM storing a user program to be rewritten based on a description of a user program for rewriting. A second process part carries out the rewriting process without regard to the data of the FLASH status 0 area. The first process part does not carry out writing on the FLASH status 0 area in the rewriting process on the first block of the flash ROM but carries out writing on the FLASH status 0 area based on the description of the user program for rewriting after carrying out the rewriting process on a last block of the flash ROM.

摘要翻译： 第一处理部分基于闪存ROM的第一块中包括的FLASH状态0区域的数据来控制包括在存储要被重写的用户程序的闪存ROM的块的擦除，写入和验证的重写处理，所述用户程序基于 描述用于重写的用户程序。 第二处理部分执行重写处理而不考虑FLASH状态0区域的数据。 第一处理部分在闪存ROM的第一块上的重写处理中不对FLASH状态0区域进行写入，而是在执行之后基于用于重写的用户程序的描述在FLASH状态0区域上执行写入 闪存ROM的最后一个块的重写过程。

公开(公告)号：EP3188189A1

公开(公告)日：2017-07-05

申请号：EP16204643.7

申请日：2016-12-16

申请人： Semiconductor Manufacturing International Corporation (Beijing) ,  Semiconductor Manufacturing International Corporation (Shanghai)

发明人： YANG, Chia Chi

IPC分类号： G11C17/16 ,  G11C17/18

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array.

摘要翻译： 电可编程熔丝（eFuse）单元阵列包括至少一个连接两个相邻eFuse单元的连接开关。 每个eFuse单元包括eFuse，用于通过写入电流的第一部分的写入开关，用于通过写入电流的第二部分或读取电流的读取/写入开关以及公共节点。 eFuse，写入开关，读取/写入开关以及至少一个连接开关在公共节点处彼此连接。 通过打开和关闭至少一个连接开关，电流在eFuse单元之间分开，从而可以减小写入开关的尺寸，从而减小阵列的总面积。