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481 条记录 (耗时 0.017 秒)

    SEMICONDUCTOR INTEGRATED CIRCUIT.
    54.
    发明公开
    SEMICONDUCTOR INTEGRATED CIRCUIT. 失效
    INTEGRIERTE HALBLEITERSCHALTUNG。

    公开(公告)号：EP0657934A4

    公开(公告)日：1997-09-03

    申请号：EP93919578

    申请日：1993-08-26

    申请人： SHIBATA TADASHI ,  OHMI TADAHIRO

    发明人： SHIBATA TADASHI ,  OHMI TADAHIRO

    IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H01L27/118 ,  H03K19/173 ,  H01L29/78

    CPC分类号： H03K19/1736 ,  H01L27/11803

    摘要： A semiconductor integrated circuit adaptable to any logic circuits using a common mask with the exception of a mask of metallic wirings so as to drastically improve performance of custom LSIs. The semiconductor integrated circuit comprises a logic circuit having a plurality of input terminals and at least one output terminal. The logic circuit includes a plurality of circuit blocks of the same circuit construction. Each of the circuit blocks has at least two stages of inverter formed by MOS semiconductor devices and at least one layer of a wiring pattern having a different pattern. The output signal of each block is defined by a predetermined function of an input signal.

    摘要翻译： 一种半导体集成电路，适用于使用除了金属布线掩模之外的共用掩模的任何逻辑电路，从而大大提高定制LSI的性能。 半导体集成电路包括具有多个输入端和至少一个输出端的逻辑电路。 逻辑电路包括具有相同电路结构的多个电路块。 每个电路块具有由MOS半导体器件形成的至少两级的反相器和至少一层具有不同图案的布线图案。 每个块的输出信号由输入信号的预定功能定义。

    Integrated circuit with gate-array interconnections routed over memory area
    55.
    发明公开
    Integrated circuit with gate-array interconnections routed over memory area 失效
    一种集成电路具有电路栅阵列的连接，这是越过存储器区域

    公开(公告)号：EP0791963A1

    公开(公告)日：1997-08-27

    申请号：EP97102404.7

    申请日：1997-02-13

    申请人： Oki Electric Industry Co., Ltd.

    发明人： Shinagawa, Noriaki

    IPC分类号： H01L27/118

    CPC分类号： H01L23/5225 ,  H01L27/118 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an integrated circuit combining a gate array with memory on a single semiconductor substrate, the interconnecting lines are routed in multiple metalization layers. In each layer having both memory and gate-array interconnecting lines, the memory interconnecting lines are routed over the memory area, and the gate-array interconnecting lines are routed in a different direction over the gate-array area. In layers having only gate-array interconnecting lines, some of these lines pass over the memory area, being routed directly above power-supply lines or shield lines provided in the layer just below.

    摘要翻译： 在在一个单一的半导体衬底相结合的存储器中的门阵列的集成电路，该互连线被布线在多个金属化层。 在具有存储器和门阵列互连线路的每个层，所述存储器互连线路路由通过存储器区域，并且门阵列互连线在栅阵列区域不同的方向上被路由。 在仅具有门阵列互连线层，其中一些论文线越过存储器区域，在上述正下方的层设置电源线或屏蔽线被直接路由。

    High density gate array cell architecture
    56.
    发明公开
    High density gate array cell architecture 失效
    Gate-Array-Zellen-Architektur hoher Dichte

    公开(公告)号：EP0782188A2

    公开(公告)日：1997-07-02

    申请号：EP96120591.1

    申请日：1996-12-20

    申请人： LSI LOGIC CORPORATION

    发明人： Park, Jonathan C.

    IPC分类号： H01L23/528 ,  H01L27/118

    CPC分类号： H01L23/528 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gate array cell architecture is provided with routing tracks at variable track pitches, thereby increasing the density of the architecture. Orientation of the devices in the gate cells perpendicularly to the routing tracks in the second metallization layer provides an increased porosity in this layer. The orientation allows an N channel device to be made smaller than a P channel device within a gate cell, to provide balanced devices. The perpendicular orientation also provides more contact points for source or drain. When the mulitple contacts are used to connect the device to a power source, the multiple contacts reduce the effective resistance and increase the reliability of the devices.

    摘要翻译： 门阵列单元架构具有可变轨道间距的路由轨迹，从而增加了体系结构的密度。 垂直于第二金属化层中的路线轨迹的门单元中的器件的取向在该层中提供了增加的孔隙率。 该方向允许使N沟道器件小于栅极单元内的P沟道器件，以提供平衡器件。 垂直方向还提供了更多的源极或漏极接触点。 当使用多个触点将设备连接到电源时，多个触点降低有效电阻并提高设备的可靠性。

    Semiconductor device with electromagnetic radiation reduced
    57.
    发明公开
    Semiconductor device with electromagnetic radiation reduced 失效
    Halbleiteranordnung mit reduzierter elektromagnetischer Strahlung

    公开(公告)号：EP0750348A1

    公开(公告)日：1996-12-27

    申请号：EP96108912.5

    申请日：1996-06-04

    申请人： NEC CORPORATION

    发明人： Igarashi, Hatuhide,c/o NEC Corporation ,  Takayama, Shigeru,c/o NEC Corporation ,  Matsuura, Yoshihiro,c/o NEC Corporation ,  Nagaishi, Hatsuhiro, NEC IC Microcomp.Systems, Ltd

    IPC分类号： H01L27/118 ,  H01L27/02

    CPC分类号： H01L27/0218 ,  H01L27/118

    摘要： In a semiconductor device in which power is supplied from an external power supply system, a first power supply system (11, 12) is connected to first terminals (1, 2) of power supply and ground and a digital inner circuit (8). The inner circuit (8) includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system (13, 14) is connected to second terminals (3, 4) of power supply and ground, the input terminal (6), the output terminal (5), and a digital interface circuit (9). The second power supply system (13, 14) is independent of the first power supply system (11, 12). The interface circuit (9) includes a MOS transistor (7) for pulling up or down the input terminal (6) and an output circuit which includes a MOS transistor driving a output terminal. The first power supply system (11, 12) is separated from the second power supply system (13, 14), and the inner circuit (8) is connected to the interface circuit (9) through only signal lines.

    摘要翻译： 在从外部电源系统供电的半导体装置中，第一电源系统（11,12）连接到电源和地线的第一端子（1,2）和数字内部电路（8）。 内部电路（8）包括时钟信号发生电路，用于时钟信号的驱动器和响应于时钟信号工作的电路。 第二电源系统（13,14）连接到电源和接地的第二端子（3,4），输入端子（6），输出端子（5）和数字接口电路（9）。 第二电源系统（13,14）独立于第一电源系统（11,12）。 接口电路（9）包括用于上拉或下降输入端子（6）的MOS晶体管（7）和包括驱动输出端子的MOS晶体管的输出电路。 第一电源系统（11,12）与第二电源系统（13,14）分离，并且内部电路（8）仅通过信号线连接到接口电路（9）。

    BiMOS integrated circuit
    58.
    发明公开
    BiMOS integrated circuit 失效
    Integrierte BiMOS-Schaltungen

    公开(公告)号：EP0735587A2

    公开(公告)日：1996-10-02

    申请号：EP96105052.3

    申请日：1996-03-29

    申请人： NEC CORPORATION

    发明人： Okamura, Hitoshi

    IPC分类号： H01L27/118

    CPC分类号： H01L27/11896

    摘要： Disclosed is a BiMOS integrated circuit, which has: a bipolar transistor for output pull-up; a BiMOS hybrid gate buffer section which comprises a MOS transistor for output pull-down which is longitudinally connected to the bipolar transistor, and a MOS transistor for base drive which comprises an output which is connected a base of the bipolar transistor to drive the base and a gate which is connected to an input; and a logical section which comprises at least a CMOS gate, the logical section having an output which is connected to the input; wherein the base drive MOS transistor has an input capacitance less than that of the output pull-down MOS transistor.

    摘要翻译： 公开了一种BiMOS集成电路，其具有：用于输出上拉的双极晶体管; BiMOS混合栅极缓冲器部分，其包括纵向连接到双极晶体管的用于输出下拉的MOS晶体管，以及用于基极驱动的MOS晶体管，其包括连接到双极晶体管的基极以驱动基极的输出，以及 连接到输入的门; 以及包括至少CMOS门极的逻辑部分，所述逻辑部分具有连接到所述输入端的输出端; 其中所述基极驱动MOS晶体管的输入电容小于所述输出下拉MOS晶体管的输入电容。

    Semiconductor device having a reduced wiring area in and out of data path zone
    60.
    发明公开
    Semiconductor device having a reduced wiring area in and out of data path zone 失效
    与内部和外部数据线区域下接合面的半导体器件。

    公开(公告)号：EP0637083A1

    公开(公告)日：1995-02-01

    申请号：EP94111976.0

    申请日：1994-08-01

    申请人： NEC CORPORATION

    发明人： Harigai, Hisao

    IPC分类号： H01L27/118 ,  H01L23/528

    CPC分类号： H01L27/118 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device formed on a semiconductor chip includes a signal processing unit composed of a plurality of signal processing cells arranged side by side in a horizontal direction, and a plurality of input/output cells each connected to a corresponding one of the signal processing cells in a one-to-one relation. The signal processing unit is located near to one corner of the semiconductor chip, and the input/output cells are uniformly distributed and located along two sides defining the above mentioned corner. Each of the signal processing cells is configured to make it possible that a wiring conductor connecting between the signal processing cell and a corresponding one of the input/output cells is taken out either in an upward vertical direction or in a downward vertical direction from the signal processing cell, in accordance with the side of the semiconductor chip along which the corresponding input/output cell is located.

    摘要翻译： 形成在半导体芯片上的半导体器件包括由侧在水平方向上并列设置的信号处理单元的多个构成的信号处理部，以及分别连接到信号处理单元中相应的一个中的输入/输出单元的多元 一比一的关系。 所述信号处理单元被靠近该半导体芯片的一个角，和输入/输出单元均匀地分布并位于沿两个侧面，定义上述角落。 每个信号处理单元被配置为使得能够做的信号处理单元和所述输入/输出单元中的相应一个之间进行连接的布线导体取出要么在垂直向上的方向或向下的垂直方向上从所述信号 处理细胞，在雅舞蹈与沿其相应的输入/输出单元位于所述半导体芯片的侧面。