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142 条记录 (耗时 0.018 秒)

    A BOUNDARY SCAN METHOD, SYSTEM AND DEVICE
    55.
    发明公开
    A BOUNDARY SCAN METHOD, SYSTEM AND DEVICE 有权
    边界扫帚，系统在EINRICHTUNG

    公开(公告)号：EP2053515A1

    公开(公告)日：2009-04-29

    申请号：EP07702184.8

    申请日：2007-01-23

    申请人： Huawei Technologies Co., Ltd.

    发明人： HUA, Sizhen

    IPC分类号： G06F11/24 ,  G01R31/3181

    CPC分类号： G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318572

    摘要： A boundary scan method, system and device, the method includes: a scan signal generating apparatus generating single polarity boundary scan signals in parallel and sending them to a boundary scan controller (S10) converting received boundary scan signals to serial differential type boundary scan signals (S11) and perfoming boundary scanning for boundary scan devices connected between a scan signal output port and a scan signal input port by converted boundary scan signals (S12). The system includes a scan signal generating apparatus, a boundary scan controller, and boundary devices. The boundary scan controller includes a data format converting module and a scan signal driving module. The boundary scan device includes a scan signal receiving module and a scan signal output module.

    摘要翻译： 一种边界扫描方法，系统和装置，所述方法包括：并行产生单极性边界扫描信号的扫描信号发生装置，并将其发送到边界扫描控制器（S10），将接收的边界扫描信号转换为串行差分型边界扫描信号 S11）和通过转换的边界扫描信号在连接在扫描信号输出端口和扫描信号输入端口之间的边界扫描装置的精确边界扫描（S12）。 该系统包括扫描信号发生装置，边界扫描控制器和边界装置。 边界扫描控制器包括数据格式转换模块和扫描信号驱动模块。 边界扫描装置包括扫描信号接收模块和扫描信号输出模块。

    MONOLITHISCH INTEGRIERTE ANPASSSCHALTUNG
    56.
    发明公开
    MONOLITHISCH INTEGRIERTE ANPASSSCHALTUNG 审中-公开
    单片集成匹配

    公开(公告)号：EP1687722A1

    公开(公告)日：2006-08-09

    申请号：EP04798060.2

    申请日：2004-11-24

    申请人： Micronas GmbH

    发明人： BIDENBACH, Reiner ,  FRANKE, Jörg ,  GIEBEL, Burkhard ,  ROGALLA, Markus

    IPC分类号： G06F11/24

    CPC分类号： G06F11/24

    摘要： The invention relates to integrated circuits comprising a monolithically integrated logic IC and a monolithically integrated interface circuit that is conductively connected to the logic IC. The electrical properties of said interface circuit are programmable. The interface circuit also has a lower integration density than the logic IC, and comprises monitoring modules for monitoring the logic ICs.

    TIMING CLOSURE MONITORING CIRCUIT AND METHOD
    57.
    发明公开
    TIMING CLOSURE MONITORING CIRCUIT AND METHOD 审中-公开
    电路及方法监控时间周期

    公开(公告)号：EP1639379A1

    公开(公告)日：2006-03-29

    申请号：EP04735779.3

    申请日：2004-06-02

    申请人： Koninklijke Philips Electronics, N.V.

    发明人： PESSOLANO, Francesco ,  THEUNISSEN, Bob, B., A.

    IPC分类号： G01R31/30 ,  G06F11/24

    CPC分类号： G01R31/31727 ,  G01R31/31725 ,  G01R31/31922 ,  G06F11/24

    摘要： An integrated circuit 1 comprises a timing closure monitoring circuit 2. The timing closure monitoring circuit 2 comprises a duplicate path 19, having the same characteristics as a logic path 3 being monitored. The duplicate path 19 receives a pulsed reference signal 23 from a reference generating unit (RGU) 24. The pulsed reference signal 23 is synchronized with the clock signal 13, and passed through the duplicate path 19 to a reference checking unit (RCU) 25. In a normal mode of operation in which timing closure is guaranteed, the clock signal 13 will sample the pulsed reference signal 23, such that no interrupt signal is generated on the interrupt line 33. However, in the situation where the reference check unit 25 is clocked by the clock signal 13 prior to the pulsed reference signal 23 being received via the duplicate path 19, an interrupt signal is generated on the interrupt line 33, indicating that timing closure cannot be guaranteed.

    A method of reducing delays
    59.
    发明公开
    A method of reducing delays 审中-公开
    Ein Verfahren zur Reduzierung vonVerzögerungen

    公开(公告)号：EP1096395A1

    公开(公告)日：2001-05-02

    申请号：EP00309134.5

    申请日：2000-10-17

    申请人： STMicroelectronics Limited

    发明人： Ballam, Peter

    IPC分类号： G06F17/50 ,  G06F11/24

    CPC分类号： G06F17/5036

    摘要： A method is described for reducing delays in an analogue simulation model of a hardware circuit. The method comprises the steps of stimulating via an input an output of said analogue model, said output and said input having a relatively high resistance therebetween and applying a pulse to a relatively low resistance, whereby when said pulse is applied to the relatively low resistance, the input is connected to said output via the relatively low resistance so that the time constant of the circuit is reduced.

    摘要翻译： 描述了一种用于减少硬件电路的模拟仿真模型中的延迟的方法。 该方法包括以下步骤：通过输入激励所述模拟模型的输出，所述输出和所述输入之间具有相对高的电阻，并将脉冲施加到相对较低的电阻，由此当所述脉冲施加到相对较低的电阻时， 该输入通过相对较低的电阻连接到所述输出端，使得电路的时间常数减小。