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    FUNCTIONALLY REDUNDANT LOGIC NETWORK ARCHITECTURES
    61.
    发明授权
    FUNCTIONALLY REDUNDANT LOGIC NETWORK ARCHITECTURES 失效
    功能冗余逻辑网络架构

    公开(公告)号：EP0165975B1

    公开(公告)日：1993-05-26

    申请号：EP85900405.3

    申请日：1984-12-10

    申请人： MOORE, Donald W. ,  VERSTRAETE, Rik A.

    发明人： MOORE, Donald W. ,  VERSTRAETE, Rik A.

    IPC分类号： H03K19/003

    CPC分类号： H03K19/1733 ,  H03K19/17708

    摘要： A logic gate structure (Fig. 4) having functionally redundant architecture for enhanced production yields and reliability comprises a plurality of two-input nodes (10) at least some of which may be programmed by control states for changing the logical function of the gate structure. Redundancy is provided by gate structure implementations in which the number of possible control states exceed the number of logic functions expected of the gate structure. Redundancy increases the probability of gate structure operation despite logic faults and renders the gate structure suitable for use in adaptable problem solving machines such as robots and pattern recognition apparatus. A number of embodiments are disclosed including three and four input variable networks (Figs. 4 and 9-16). Some such embodiments include selected architectural simplifications wherein certain nodes in a network are either logically fixed or entirely omitted to reduce the number of control lines.

    PROGRAMMABLE LOGIC DEVICE WITH PROGRAMMABLE INVERTERS AT INPUT/OUTPUT PADS
    62.
    发明公开
    PROGRAMMABLE LOGIC DEVICE WITH PROGRAMMABLE INVERTERS AT INPUT/OUTPUT PADS 失效
    与可编程变频器到输入/输出端子可编程逻辑器件。

    公开(公告)号：EP0517846A1

    公开(公告)日：1992-12-16

    申请号：EP91906333.0

    申请日：1991-02-22

    申请人： PLUS LOGIC, INC.

    发明人： KAPLINSKY, Cecil, H.

    IPC分类号： H03K19

    CPC分类号： H03K19/1736 ,  H03K19/17708

    摘要： Un dispositif logique programmable (15) comprend une pluralité d'unités fonctionnelles (4), une matrice (3) programmable d'interconnexion des unités fonctionnelles, des broches d'entrée (24) et de sortie (26) couplées à la matrice d'interconnexion et des inverseurs programmables (25, 27) connectés entre les broches et des lignes conductrices (19) de la matrice afin d'inverser des signaux extérieurs qui entrent dans la matrice d'interconnexion ou qui en sortent. Chaque unité fonctionnelle (4) peut en elle-même constituer un dispositif logique programmable avec des entrées, avec un réseau ET connecté aux entrées, ou un réseau OU connecté au réseau ET, des registres optiques et des inverseurs du côté de sortie du réseau OU, et des sorties couplées au réseau OU, aux registres ou aux inverseurs. La matrice programmable (3) d'interconnexion comprend deux ensembles de lignes conductrices (19) qui s'intersectent et qui peuvent être connectées par des liaisons programmables à chaque intersection. Les lignes sont connectées aux entrées des unités fonctionnelles et à des broches d'entrée et de sortie.

    Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks
    63.
    发明公开
    Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks 失效
    具有多个可编程逻辑阵列的可编程逻辑器件安装在具有多个互连的接口块的MOSAIC布局中

    公开(公告)号：EP0376905A3

    公开(公告)日：1992-05-27

    申请号：EP89830569.3

    申请日：1989-12-22

    申请人： SGS-THOMSON MICROELECTRONICS S.r.l.

    发明人： Benedetti, Mirella ,  Chiriatti, Antonio ,  Daniele, Vincenzo ,  Giacalone, Biagio

    IPC分类号： H03K19/177

    CPC分类号： H03K19/1735 ,  H03K19/17708 ,  H03K23/542

    摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multi­levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multifunctional blocks.

    Programmable logic device power controller
    64.
    发明公开
    Programmable logic device power controller 失效
    可编程逻辑器件功率控制器

    公开(公告)号：EP0456374A3

    公开(公告)日：1992-04-15

    申请号：EP91303673.7

    申请日：1991-04-24

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Trinh, Cuong O. ,  Win, Vincent ,  Kwan, Mark

    IPC分类号： H03K19/177 ,  H03K19/00

    CPC分类号： H03K19/0016 ,  H03K19/17708

    摘要： An apparatus for controlling power in a programmable array logic device, particularly a programmable array logic device (PAL) having a plurality of programmable product terms, is provided. The apparatus comprises a programmable switch coupled to at least one of the programmable product term outputs for selectively enabling the logic signal output therefrom. Each such programmable switch may include: an amplifier (SA) having an inverting input coupled to one of the programmable product term outputs; a first transistor (12) coupled between the amplifier and ground; a first inverter (14) coupled to the first transistor; a latch (20) coupled to the first inverter; a second transistor (26) coupled to the latch; a power-up reset circuit (10) coupled to the second transistor; and an electrically erasable programmable read only memory cell (28) coupled to the second transistor and latch means. Also provided is a method for controlling the power consumption of a PAL which includes a plurality of programmable product term outputs. The method comprises selectively enabling each of a plurality of sense amplifier means, each one of the plurality of amplifier means being coupled to one of the product term outputs. Each amplifier is enabled using a separate control signal input to selectively enable each of said plurality of said amplifier means upon power-up of the programmable logic device.

    PROGRAMMABLE LOGIC EXPANDER
    65.
    发明公开
    PROGRAMMABLE LOGIC EXPANDER 失效
    逻辑扩展可编程器件。

    公开(公告)号：EP0472650A1

    公开(公告)日：1992-03-04

    申请号：EP90908864.0

    申请日：1990-05-09

    申请人： PLUS LOGIC, INC.

    发明人： KAPLINSKY, Cecil, H.

    IPC分类号： H03K19

    CPC分类号： H03K19/17708

    摘要： Un dispositif logique programmable comprend des portes ET connectées à des portes OU, qui à leur tour sont connectées à un troisième niveau logique, constitué par un module d'extension logique (121, 123). Le module permet de sélectionner de manière programmable une fonction logique parmi 16 fonctions logiques à une et à deux variables ou parmi 256 fonctions logiques à une, deux et trois variables. Dans un mode de réalisation (11, 61), des portes logique telles que ET, OU, OU exclusif ou d'inversion assurent les fonctions logiques. Dans un deuxième mode de réalisation (91), ainsi que dans un troisième mode de réalisation, une table à consulter et une série de transistors de passage assurent respectivement les fonctions logiques.

    A programmable logic array
    69.
    发明公开
    A programmable logic array 失效
    可编程逻辑阵列

    公开(公告)号：EP0256336A3

    公开(公告)日：1989-11-02

    申请号：EP87110545.8

    申请日：1987-07-21

    申请人： International Business Machines Corporation

    发明人： Masleid, Robert Paul ,  Schmookler, Martin Stanley

    IPC分类号： H03K19/177

    CPC分类号： H03K19/01721 ,  H03K19/17708

    摘要： A programmable logic array comprises:
        a plurality of electrically isolated input lines (eg 204, 206, 208, 210);
        input means (200) for addressing the plurality of input lines and directing an input signal to an addressed one thereof;
        a plurality of electrically isolated output lines (220, 228) positioned to form a plurality of nonconductive intersections with said input lines;
        an individual transistor (212, 214, 216, 218, 230, 232, 234, 236) disposed at each intersection, the control electrode of the transistor being connected to one of the input lines and one current flow electrode of the transistor being connected to one of the output lines and the other current flow electrode of the transistor being connected to a selected one of two potential sources (GND, +V), the selection being made in the course of programming the array, whereby a programmed output signal is obtained on the output line to which said one currant flow electrode is connected when an input signal is directed to an addressed input line.

    Programmable logic array with added array of gates and added output routing flexibility
    70.
    发明公开
    Programmable logic array with added array of gates and added output routing flexibility 失效
    可编程逻辑阵列与增加的门阵列和增加的输出路由灵活性

    公开(公告)号：EP0213971A3

    公开(公告)日：1988-12-14

    申请号：EP86401085

    申请日：1986-05-22

    申请人： Monolithic Memories, Inc.

    发明人： Birkner, John ,  Chua, Hua Thye ,  Chan, Andrew K.L. ,  Chan, Albert

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17708 ,  H03K19/17712

    摘要： A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1 through 102-66). The output signals from the first set of AND gates are programmably elec­trically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are program­mably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coup­led to each of the output signals from the second OR logic array and the output pins (O₁ through O₁₀) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.