公开(公告)号：EP0789312A1

公开(公告)日：1997-08-13

申请号：EP97300828.7

申请日：1997-02-07

申请人： SHARP KABUSHIKI KAISHA

发明人： Iizuka, Kunihiko

IPC分类号： G06G7/12

CPC分类号： G06G7/12

摘要： An analog arithmetic unit furnished with an input capacitor, an amplifier, a floating gate MOS. An input voltage is given to the amplifier through the input capacitor. The amplifier is composed of a CMOS inverter or the like and has a floating gate in a node at its input end. The floating gate MOS controls an amount of charges in the above node by injecting the hot electrons or absorbing the charges through the tunnel effect. Accordingly, it has become possible to maintain an amount of charges at the above node at a constant level over a long period. Thus, a frequency at which an offset voltage caused by charges accumulated at the above floating gate and causing an operation error can be reduced, thereby increasing an overall arithmetic operation.

摘要翻译： 一个模拟运算装置，在输入电容器配有，在放大器，浮栅MOS。 输入电压被提供给通过所述输入电容器的放大器。 该放大器是由CMOS反相器或类似的并具有一个浮置栅极中在其输入端的节点。 浮栅MOS通过注入热电子或吸收通过隧道效应的电荷上的上述节点中的电荷量控制。 因此，它已成为可以对在上述节点中的电荷量保持在恒定水平在长时间内。 因此，频率在其处偏移电压由在上述浮置栅极积累并造成到operationsError电荷引起的可被减小，从而提高了总体的算术运算。

公开(公告)号：EP0268182B1

公开(公告)日：1994-08-10

申请号：EP87116529.6

申请日：1987-11-09

申请人： OMRON TATEISI ELECTRONICS CO.

发明人： Yamakawa, Takeshi

IPC分类号： G06F7/60 ,  G06G7/12

CPC分类号： G06N7/043 ,  Y10S706/90

公开(公告)号：EP0539246A3

公开(公告)日：1994-03-09

申请号：EP92402532.3

申请日：1992-09-16

申请人： GOVERNMENT OF THE UNITED STATES OF AMERICA as represented by THE ADMINISTRATOR OF THE NATIONAL AERONAUTICS AND SPACE ADM.

发明人： Salazar, George A.

IPC分类号： H03M1/34 ,  H03M1/46 ,  G06F12/00 ,  G06F15/46 ,  H03K19/00 ,  H03K19/20 ,  G05B13/02 ,  G06G7/12

CPC分类号： G06N7/023 ,  G06N7/04 ,  Y10S706/90

摘要： A reconfigurable fuzzy cell comprising a digital control programmable gain operation amplifier, an analog-to-digital converter, an electrically erasable PROM, and 8-bit counter and comparator, and supporting logic configured to achieve in real-time fuzzy systems high throughput, grade-of-membership or membership-value conversion of multi-input sensor data. The present invention provides a flexible multiplexing-capable configuration, implemented entirely in hardware, for effectuating S-, Z-, and PI-membership functions or combinations thereof, based upon fuzzy logic level-set theory. A membership value table storing "knowledge-data" for each of S-, Z-, and PI-functions is contained within a nonvolatile memory for storing bits of membership and parametric information in a plurality of address spaces. Based upon parametric and control signals, analog sensor data is digitized and converted into grade-of-membership data. In situ learn and reconfiguration modes of operation are also provided.

摘要翻译： 包括数字控制可编程增益运算放大器，模数转换器，电可擦除PROM和8位计数器和比较器的可重新配置模糊单元以及配置为实现实时模糊系统的高吞吐量，等级 多输入传感器数据的成员资格或成员资格转换。 本发明提供了一种灵活的多路复用的配置，完全以硬件实现，用于基于模糊逻辑电平集理论实现S，Z和PI隶属函数或其组合。 存储用于S，Z和PI功能中的每一个的“知识数据”的成员关系值表被包含在用于在多个地址空间中存储成员资格和参数信息的位的非易失性存储器内。 基于参数和控制信号，模拟传感器数据被数字化并转换成等级数据。 还提供了原位学习和重新配置操作模式。

公开(公告)号：EP0502701A2

公开(公告)日：1992-09-09

申请号：EP92301826.1

申请日：1992-03-04

申请人： MIKUNI CORPORATION

发明人： Muraji, Tetsuo, c/o Mikuni Corporation

IPC分类号： G06G7/12

CPC分类号： G06N7/043 ,  Y10S706/90

摘要： A circuit is disclosed for deriving an output which is indicative of the centre of gravity of electric signals representative of fuzzy information distributed over a plurality of lines. In one embodiment the circuit comprises a weighted summing circuit which forms a sum from the signals after multiplying each signal by a respective value corresponding to the grade of its said line, and a simple summing integration circuit which executes summing integration of the electric signals without any weighting. In an alternative embodiment the circuit comprises a weight summing integration circuit which executes summing integration of the signals after multiplying each such signal by a respective value corresponding to the grade of its line, and a simple summing circuit that simply sums the signals without weighting. In both embodiments a comparator then makes a comparison between the outputs of the two circuits.

摘要翻译： 公开了一种用于导出表示代表分布在多条线上的模糊信息的电信号的重心的输出的电路。 在一个实施例中，该电路包括加权求和电路，该加权求和电路在将每个信号乘以与其所述线的等级对应的相应值之后的信号中形成一个和，以及一个简单求和积分电路，其执行电信号的相加积分而没有任何 权重。 在替代实施例中，电路包括权重求和积分电路，其在将每个这样的信号乘以与其线的等级相对应的相应值之后执行信号的求和积分，以及简单地求和信号而不加权的简单求和电路。 在两个实施例中，比较器然后对两个电路的输出进行比较。

公开(公告)号：EP0268182A3

公开(公告)日：1991-07-10

申请号：EP87116529.6

申请日：1987-11-09

申请人： OMRON TATEISI ELECTRONICS CO.

发明人： Yamakawa, Takeshi

IPC分类号： G06F7/60 ,  G06G7/12

CPC分类号： G06N7/043 ,  Y10S706/90

摘要： A fuzzy computer basically includes a plurality of fuzzy membership function generator circuits (43, 43A, 43B, 43C, 43D), and a fuzzy inference engine (50, 51) for executing a predetermined fuzzy operation among fuzzy membership functions that have been generated. A fuzzy membership function is represented by electric signal distributed on a plurality of lines.

公开(公告)号：EP0114314B1

公开(公告)日：1990-05-23

申请号：EP83112677.6

申请日：1983-12-16

申请人： INTERSIL, INC.

发明人： Bingham, David ,  Evans, Lee Leland ,  Bradshaw, Peter Duncan

IPC分类号： G06G7/12

CPC分类号： H03F3/45977 ,  G06G7/14 ,  G06G7/161 ,  G06G7/1865 ,  H03F2200/261 ,  H03F2203/45551

公开(公告)号：EP0162225A1

公开(公告)日：1985-11-27

申请号：EP85103414.0

申请日：1985-03-22

申请人： OMRON TATEISI ELECTRONICS CO.

发明人： Ueno, Fumio ,  Yamakawa, Takeshi ,  Shirai, Yuji

IPC分类号： G06G7/12 ,  H03K19/094 ,  H03K5/24

CPC分类号： G06N7/043 ,  H01L27/0629 ,  H01L27/11807 ,  H03K19/00 ,  H03K19/094

摘要： A fuzzy logic circuit comprising a current mirror (1) comprising a FET, a first input current source (4) connected to the input side of the current mirror (1), a second input current source (3), a wired OR (7) connected at its input side to the output side of the current mirror (1) and to the second input current source (3), and an output terminal (5) connected to the output side of the wired OR (7).

摘要翻译： 一种模糊逻辑电路，包括电流镜（1），包括FET，连接到电流镜（1）的输入侧的第一输入电流源（4），第二输入电流源（3），有线OR ）连接到电流镜（1）的输出侧和第二输入电流源（3），以及连接到有线OR（7）的输出侧的输出端子（5）。