BULB-SHAPED MEMORY STACK STRUCTURES FOR DIRECT SOURCE CONTACT IN THREE-DIMENSIONAL MEMORY DEVICE

    公开(公告)号:EP4040490A1

    公开(公告)日:2022-08-10

    申请号:EP22164201.0

    申请日:2017-09-07

    摘要: The contact area between a source strap structure of a buried source layer and semiconductor channels within memory structures can be increased by laterally expanding a source-level volume in which the memory stack structures are formed. In one embodiment, sacrificial semiconductor pedestals can be formed in source-level memory openings prior to formation of a vertically alternating stack of insulating layers and sacrificial material layers. Memory openings can include bulging portions formed by removal of the sacrificial semiconductor pedestals. Memory stack structures can be formed with a greater sidewall surface area in the bulging portions to provide a greater contact area with the source strap structure. Alternatively, bottom portions of memory openings can be expanded selective to upper portions during, or after, formation of the memory openings to provide bulging portions and to increase the contact area with the source strap structure.

    THREE-DIMENSIONAL MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

    公开(公告)号:EP4016627A1

    公开(公告)日:2022-06-22

    申请号:EP21151887.3

    申请日:2021-01-15

    摘要: A three-dimensional memory device and a method for manufacturing the same are provided. The three-dimensional memory device includes a plurality of tiles, and each tile includes a plurality of blocks, and each block includes a gate stacked structure, a conductive layer, first ring-shaped channel pillars, source/drain pillars, and charge storage structures. The gate stacked structure disposed on the substrate includes gate layers electrically insulated from each other. The conductive layer is disposed between the substrate and the gate stacked structure. The first ring-shaped channel pillars are disposed on the substrate and located in the gate stacked structure. Each of the first ring-shaped channel pillars is configured with two source/drain pillars disposed therein. Each of the charge storage structures is disposed between the corresponding gate layer and the corresponding first ring-shaped channel pillar. The conductive layer in one of the tiles is isolated from the conductive layers in the other tiles.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:EP3975255A1

    公开(公告)日:2022-03-30

    申请号:EP21182547.6

    申请日:2021-06-29

    摘要: A semiconductor device and an electronic system are disclosed. The semiconductor device includes a semiconductor substrate; a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuits; a semiconductor layer on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor layer, the metal structure including first portions extending in a first direction, second portions connected to the first portions and extending in a second direction crossing the first direction, and a via portion vertically extending from at least one of the first and second portions and being connected to the landing pad; and a stack including insulating layers and electrodes vertically and alternately stacked on the metal structure.