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    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTILEVEL DRAIN SELECT GATE ISOLATION AND METHODS OF MAKING THE SAME
    2.
    发明公开
    THREE-DIMENSIONAL MEMORY DEVICE CONTAINING MULTILEVEL DRAIN SELECT GATE ISOLATION AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：EP3876276A2

    公开(公告)日：2021-09-08

    申请号：EP21165030.4

    申请日：2019-02-28

    申请人： SanDisk Technologies LLC

    发明人： NISHIKAWA, Masatoshi ,  YADA, Shinsuke ,  ZHANG, Yanli

    IPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11524

    摘要： A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

    ARRAY OF PILLARS LOCATED IN A UNIFORM PATTERN
    3.
    发明公开
    ARRAY OF PILLARS LOCATED IN A UNIFORM PATTERN 审中-公开

    公开(公告)号：EP3726577A1

    公开(公告)日：2020-10-21

    申请号：EP19173569.5

    申请日：2019-05-09

    申请人： MACRONIX INTERNATIONAL CO., LTD.

    发明人： LAI, Erh-Kun ,  LUNG, Hsiang-Lan

    IPC分类号： H01L27/11565 ,  H01L27/11582

    摘要： A memory device comprises a stack of conductive layers, and an array of pillars through the stack. Each of the pillars comprises a plurality of series-connected memory cells located in a layout pattern of pillar locations at cross-points between the pillars and the conductive layers. The pillars in the array are arranged in a set of rows of pillars extending in a first direction. First and second source lines are disposed vertically through the pillars of first and second particular rows of pillars. The set of rows of pillars includes a subset of rows of pillars including multiple members disposed between the first source line and the second source line. A source line conductor is disposed beneath and electrically connected to the first source line, the second source line, and the subset of rows of pillars disposed between the first and second source lines.

    WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY
    9.
    发明公开
    WORD LINE DECODER CIRCUITRY UNDER A THREE-DIMENSIONAL MEMORY ARRAY 审中-公开

    公开(公告)号：EP3375012A1

    公开(公告)日：2018-09-19

    申请号：EP16823449.0

    申请日：2016-12-19

    申请人： SanDisk Technologies LLC

    发明人： OGAWA, Hiroyuki ,  TOYAMA, Fumiaki ,  ARIKI, Takuya

    IPC分类号： H01L27/11519 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11578

    摘要： The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    10.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
    半导体器件和制造半导体器件的方法

    公开(公告)号：EP3136424A2

    公开(公告)日：2017-03-01

    申请号：EP16184770.2

    申请日：2016-08-18

    申请人： Renesas Electronics Corporation

    发明人： Arigane, Tsuyoshi ,  Hisamoto, Digh

    IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

    CPC分类号： H01L27/1157 ,  H01L21/28282 ,  H01L21/32133 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42368 ,  H01L29/66833 ,  H01L29/792

    摘要： A property of a semiconductor device having a non-volatile memory is improved. A semiconductor device, which has a control gate electrode part and a memory gate electrode part placed above a semiconductor substrate of a non-volatile memory, is configured as follows. A thick film portion is formed in an end portion of the control gate insulating film on the memory gate electrode part side, below the control gate electrode part. According to this configuration, even when holes are efficiently injected to a comer portion of the memory gate electrode part by an FN tunnel erasing method, electrons can be efficiently injected to the comer portion of the memory gate electrode part by an SSI injection method. Thus, a mismatch of the electron/hole distribution can be moderated, so that the retention property of the memory cell can be improved.

    摘要翻译： 具有非易失性存储器的半导体器件的特性得到改善。 具有控制栅极电极部分和设置在非易失性存储器的半导体衬底上方的存储器栅极电极部分的半导体器件如下配置。 在控制栅极电极部分下方的存储器栅极电极部分侧上的控制栅极绝缘膜的端部中形成厚膜部分。 根据该结构，即使通过FN隧道擦除法将空穴高效率地注入存储器栅极电极部的角部，也能够通过SSI注入法将电子高效率地注入存储器栅极电极部的角部。 因此，可以缓和电子/空穴分布的不匹配，从而可以提高存储单元的保持特性。