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公开(公告)号：EP4130988A1
公开(公告)日：2023-02-08
申请号：EP22198615.1
申请日：2020-03-14
申请人： INTEL Corporation
发明人： Koker, Altug , Ray, Joydeep , Ould-Ahmed-Vall, ElMoustapha , Appu, Abhishek , Anantaraman, Aravindh , Andrei, Valentin , Bilagi, Durgaprasad , George, Varghese , Insko, Brent , Jahagirdar, Sanjeev , Janus, Scott , K, Pattabhiraman , Kim, SungYe , Maiyuran, Subramaniam , Ranganathan, Vasanth , Striramassarma, Lakshminarayanan , Tian, Xinmin
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/0891
摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor comprises processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to, in response to an instruction executed by one of the processing resources, modify an aging policy by modifying, based on the instruction, a level of importance from a first level of importance to preserve data longer in the cache for a first time period to a second level of importance for data to be evicted from the cache within a second time period, which is less than the first time period.
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62.发明公开
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63.发明公开
公开(公告)号：EP4121850A1
公开(公告)日：2023-01-25
申请号：EP20725485.5
申请日：2020-05-08
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公开(公告)号：EP4109243A1
公开(公告)日：2022-12-28
申请号：EP22162082.6
申请日：2022-03-15
申请人： Intel Corporation
发明人： Gurram, Chandra , Chen, Wei-Yu , Vemulapalli, Vikranth , Maiyuran, Subramaniam , Parra, Jorge , Mu, Shuai , Lueh, Guei-Yuan , Pal, Supratim
摘要： Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.
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公开(公告)号：EP4100830A1
公开(公告)日：2022-12-14
申请号：EP21750108.9
申请日：2021-02-01
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公开(公告)号：EP4091049A1
公开(公告)日：2022-11-23
申请号：EP20913888.2
申请日：2020-01-13
发明人： WESSLÉN, Anders , BRESCHEL, Michael
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公开(公告)号：EP4085328A1
公开(公告)日：2022-11-09
申请号：EP20845758.0
申请日：2020-12-30
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公开(公告)号：EP4083789A1
公开(公告)日：2022-11-02
申请号：EP22171943.8
申请日：2018-05-17
申请人： Google LLC
摘要： Methods, systems, and apparatus including a special purpose hardware chip for training neural networks are described. The special-purpose hardware chip may include a scalar processor configured to control computational operation of the special-purpose hardware chip. The chip may also include a vector processor configured to have a 2-dimensional array of vector processing units which all execute the same instruction in a single instruction, multiple-data manner and communicate with each other through load and store instructions of the vector processor. The chip may additionally include a matrix multiply unit that is coupled to the vector processor configured to multiply at least one two-dimensional matrix with a second one-dimensional vector or two-dimensional matrix in order to obtain a multiplication result.
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