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    METHOD AND APPARATUS FOR GENERATING NB-IOT OFDM SIGNALS WITH A LOWER SAMPLING RATE
    2.
    发明公开
    METHOD AND APPARATUS FOR GENERATING NB-IOT OFDM SIGNALS WITH A LOWER SAMPLING RATE 审中-公开

    公开(公告)号：EP3417547A1

    公开(公告)日：2018-12-26

    申请号：EP17703079.8

    申请日：2017-01-27

    申请人： Telefonaktiebolaget LM Ericsson (PUBL)

    发明人： HILL, Johan ,  BRESCHEL, Michael

    IPC分类号： H03M1/00 ,  H04L5/00 ,  H04L27/26

    CPC分类号： H04L27/2607 ,  H03M1/004 ,  H03M1/66 ,  H04L5/0037

    摘要： A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

    BLIND RATE DETECTION IN A MULTIPLEXED TRANSMISSION SYSTEM
    3.
    发明授权
    BLIND RATE DETECTION IN A MULTIPLEXED TRANSMISSION SYSTEM 有权
    盲速率检测多路传输系统

    公开(公告)号：EP1219084B1

    公开(公告)日：2006-11-15

    申请号：EP00962530.2

    申请日：2000-09-26

    申请人： TELEFONAKTIEBOLAGET LM ERICSSON (publ)

    发明人： PALENIUS, Torgny ,  BRESCHEL, Michael

    IPC分类号： H04L25/02 ,  H04L1/00

    CPC分类号： H04L25/0262 ,  H04L1/0046 ,  H04L1/0061

    摘要： Data is multiplexed in a frame having a fixed bit length in a telecommunication system. The data is transmitted by transmitting a first transport channel comprising a first number of bits; transmitting first error detection bits associated with the first transport channel and comprising a second number of bits; transmitting a second transport channel comprising a third number of bits; transmitting a third transport channel comprising a fourth number of bits; and selectively transmitting a control channel comprising a fifth number of bits. The control channel is transmitted after the first error detection bits and before transmission of the third transport channel. Whenever the control channel is transmitted as part of the frame, a sum of the first, second, third, fourth and fifth number of bits equals the fixed bit length, but whenever the control channel is not transmitted as part of the frame, a sum of the first, second, third and fourth number of bits equals the fixed bit length.

    RECEIVER CIRCUIT AND METHODS
    10.
    发明公开
    RECEIVER CIRCUIT AND METHODS 审中-公开

    公开(公告)号：EP3417546A1

    公开(公告)日：2018-12-26

    申请号：EP17705109.1

    申请日：2017-02-14

    申请人： Telefonaktiebolaget LM Ericsson (PUBL)

    发明人： LIU, Yuhang ,  AXMON, Joakim ,  BRESCHEL, Michael ,  HILL, Johan

    IPC分类号： H03L7/099 ,  H04B1/40

    CPC分类号： H03M1/0624 ,  H03L7/0996 ,  H03M1/1255 ,  H03M1/46 ,  H04B1/16 ,  H04B1/40 ,  H04L27/2689

    摘要： Disclosed is a receiver circuit comprising an analog-to-digital converter (ADC) circuit having an analog input, a clock input, and a digital output, and a clock divider circuit having a reference clock input and a phase selector input, and having a clock output coupled to the clock input of the ADC circuit. The clock divider circuit is configured to divide a reference clock signal coupled to the reference clock input at a reference clock frequency, to produce a clock output signal at an ADC clock frequency, at the clock output, such that the reference clock frequency is an integer multiple N of the ADC clock frequency. The clock divider circuit is further configured to select from among a plurality of selectable phases of the clock output signal, responsive to a phase selector signal applied to the phase selector input.