公开(公告)号：EP3964969A1

公开(公告)日：2022-03-09

申请号：EP21204670.0

申请日：2020-01-23

申请人： INTEL Corporation

发明人： Matam, Naveen ,  Cheney, Lance ,  Finley, Eric ,  George, Varghese ,  Jahagirdar, Sanjeev ,  Koker, Altug ,  Mastronarde, Josh ,  Rajwani, Iqbal ,  Striramassarma, Lakshminarayanan ,  Teshome, Melaku ,  Vemulapalli, Vikranth ,  Xavier, Binoj

IPC分类号： G06F13/40 ,  H01L25/11 ,  H01L25/065 ,  H01L25/18

摘要： The present disclosure provides an apparatus comprising a package assembly comprising a plurality of chiplets and a plurality of interconnect structures. The plurality of chiplets including a first chiplet comprising a first base chiplet coupled to a bridge interconnect and an interconnect structure. The first base chiplet including an interconnect fabric, and a first plurality of level 3 cache banks to cache data read from and transmitted to a memory, a second chiplet comprising a second base chiplet, the second chiplet coupled to the first chiplet over the bridge interconnect; and a third chiplet including a second plurality of level 3 cache banks, the third chiplet stacked on the first base chiplet in a 3D arrangement and coupled to the first base chiplet over the interconnect structure.

公开(公告)号：EP4328971A3

公开(公告)日：2024-05-15

申请号：EP24150728.4

申请日：2020-01-23

申请人： INTEL Corporation

发明人： Matam, Naveen ,  Cheney, Lance ,  Finley, Eric ,  George, Varghese ,  Jahagirdar, Sanjeev ,  Koker, Altug ,  Mastronarde, Josh ,  Rajwani, Iqbal ,  Striramassarma, Lakshminarayanan ,  Teshome, Melaku ,  Vemulapalli, Vikranth ,  Xavier, Binoj

IPC分类号： G06F13/40 ,  H01L25/11 ,  H01L25/065 ,  H01L25/18

CPC分类号： G06F13/4068 ,  G06F13/409 ,  H01L2224/1622720130101 ,  H01L2924/1531120130101 ,  H01L25/0655 ,  H01L25/18 ,  H01L2924/1519220130101 ,  Y02D10/00

摘要： The present disclosure provides an apparatus comprising a package assembly that includes a first base chiplet, a first logic chiplet stacked on the first base chiplet, a first interconnect structure to couple the cluster of compute units to the first interconnect fabric, a second base chiplet coupled to the first base chiplet by a second interconnect structure, a second logic chiplet stacked on the second base chiplet, and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric. In the provided apparatus, the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets.

公开(公告)号：EP4328971A2

公开(公告)日：2024-02-28

申请号：EP24150728.4

申请日：2020-01-23

申请人： INTEL Corporation

发明人： Matam, Naveen ,  Cheney, Lance ,  Finley, Eric ,  George, Varghese ,  Jahagirdar, Sanjeev ,  Koker, Altug ,  Mastronarde, Josh ,  Rajwani, Iqbal ,  Striramassarma, Lakshminarayanan ,  Teshome, Melaku ,  Vemulapalli, Vikranth ,  Xavier, Binoj

IPC分类号： H01L25/11

摘要： The present disclosure provides an apparatus comprising a package assembly that includes a first base chiplet, a first logic chiplet stacked on the first base chiplet, a first interconnect structure to couple the cluster of compute units to the first interconnect fabric, a second base chiplet coupled to the first base chiplet by a second interconnect structure, a second logic chiplet stacked on the second base chiplet, and a third interconnect structure to couple the second logic chiplet to the second interconnect fabric. In the provided apparatus, the first logic chiplet is manufactured using a different process technology than that used to manufacture the first and second base chiplets.

公开(公告)号：EP4109243A1

公开(公告)日：2022-12-28

申请号：EP22162082.6

申请日：2022-03-15

申请人： Intel Corporation

发明人： Gurram, Chandra ,  Chen, Wei-Yu ,  Vemulapalli, Vikranth ,  Maiyuran, Subramaniam ,  Parra, Jorge ,  Mu, Shuai ,  Lueh, Guei-Yuan ,  Pal, Supratim

IPC分类号： G06F9/30 ,  G06F9/38

摘要： Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.