公开(公告)号：EP0175342A2

公开(公告)日：1986-03-26

申请号：EP85111733.3

申请日：1985-09-17

申请人： Honeywell Bull Inc.

发明人： Murray, Thomas L. ,  Holtey, Thomas O. ,  Bruce, Kenneth E.

IPC分类号： G09G1/16

CPC分类号： G09G5/40 ,  G09G5/30

摘要： The invention pertains to a method and hardware for adding graphics capability to an existing alphanumeric computer system by providing graphics generation logic to existing alphanumeric generation logic and mixing and synchronizing the graphics data to the normal text display data.

摘要翻译： 本发明涉及一种用于通过向现有的字母数字生成逻辑提供图形生成逻辑并将图形数据混合并同步到正常文本显示数据来将图形能力添加到现有的字母数字计算机系统的方法和硬件。

公开(公告)号：EP0170977A2

公开(公告)日：1986-02-12

申请号：EP85109248.6

申请日：1985-07-24

申请人： Honeywell Bull Inc.

发明人： Bruce, Kenneth E. ,  Holtey, Thomas ,  Goss, Gary J.

IPC分类号： G09G1/16

CPC分类号： G09G5/393

摘要： A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

摘要翻译： 具有图形能力的显示子系统包括用于存储位的位图存储器，每个位表示显示的像素。 只读存储器存储单词，表示所选图案的像素的每个单词用于填充显示区域，从而将显示器的相邻区域清楚地识别给操作者。 选择的模式以REPLACE，OR或EXCLUSIVE OR操作模式显示。

公开(公告)号：EP0131277A2

公开(公告)日：1985-01-16

申请号：EP84107914.8

申请日：1984-07-06

申请人： Honeywell Bull Inc.

发明人： Hooker, Lane K. ,  Howell, Thomas H. ,  Ferrell, Charles W.

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/084

摘要： A multiple processor computer system features a store-into cache arrangement wherein each processor unit of the system has its own unique cache memory unit. Data operated upon by any one of the processor units is stored in the cache memory associated with that processor unit. When a thus modified block of data is required by another one of the processor units, the requested data is transferred directly to the requesting processor unit without having to first transfer the data to a shared main memory. Provision is also made for transferring data, under prescribed conditions from a cache to the main memory, but not as a precondition for transfer to a requesting processor.

摘要翻译： 多处理器计算机系统具有存储到高速缓存装置，其中系统的每个处理器单元具有其自己的唯一高速缓冲存储器单元。 由任何一个处理器单元操作的数据被存储在与该处理器单元相关联的高速缓冲存储器中。 当另一个处理器单元需要如此修改的数据块时，将所请求的数据直接传送到请求处理器单元，而不必首先将数据传送到共享的主存储器。 还规定了在规定的条件下将数据从缓存传输到主存储器，但不作为传送到请求处理器的前提条件。

公开(公告)号：EP0076629A2

公开(公告)日：1983-04-13

申请号：EP82305140.4

申请日：1982-09-29

申请人： Honeywell Bull Inc.

发明人： Johnson, Robert B. ,  Salas, Edward R. ,  Nibby, Chester M., Jr.

IPC分类号： G06F11/20 ,  G06F12/06

CPC分类号： G11C29/76 ,  G06F11/006 ,  G06F12/0661

摘要： A memory system comprises a plurality of controllers each of which controls two pairs of daughter boards, each daughter board containing a quarter of the total memory of the controller. Each controller has a set of manually settable switches defining its identity (top end of memory address). Each controller includes reconfiguration apparatus which can be set, by reconfiguration commands, to store a new identity number and use that instead of the manually set number. Further reconfiguration command bits can control the effective arrangement of the daughter boards, dependent on whether the controller is half or fully populated, to put faulty ones off-line. Thus on a memory fault, the complete memory space may be maintained by reconfiguring the controllers within the memory space required.

公开(公告)号：EP0076155A2

公开(公告)日：1983-04-06

申请号：EP82305139.6

申请日：1982-09-29

申请人： Honeywell Bull Inc.

发明人： Salas, Edward R. ,  Nibby, Chester M., Jr. ,  Johnson, Robert B.

IPC分类号： G11C8/00 ,  G11C11/24 ,  G06F13/00

CPC分类号： G06F12/04 ,  G11C8/04 ,  G11C11/4063

摘要： A memory system includes at least a pair of independently addressable dynamic memory module units, each of which includes a number of rows of random access memory (RAM) chips. The subsystem further includes an adder circuit, a pair of tristate operated address register circuits and timing circuits. The address circuits include a pair of tristate operated address registers coupled to the set of address lines of each memory unit. In response to a memory request, these registers store row and column address portions of a chip address, which are fed in succession to the chips. A multibit adder circuit increments by 1 the low order column address portion when the least significant address bit of the memory request indicates a subboundary address condition, thereby enabling access to a pair of sequential word locations. Whenever a memory request specifies an address which cannot access a double word, boundary circuits detect the condition and cause the timing circuits to generate only the timing signals necessary for accessing the first word location.

摘要翻译： 一种存储器系统包括至少一对可独立寻址的动态存储器模块单元，每个动态存储器模块单元包括若干行随机存取存储器（RAM）芯片。 该子系统还包括加法器电路，一对三态操作的地址寄存器电路和定时电路。 地址电路包括耦合到每个存储器单元的一组地址线的一对三态操作地址寄存器。 响应于存储器请求，这些寄存器存储芯片地址的行地址部分和列地址部分，这些地址部分被连续地馈送到芯片。 当存储器请求的最低有效地址位指示子边界地址条件时，多位加法器电路将低位列地址部分递增1，由此使得能够访问一对顺序字位置。 无论何时存储器请求指定不能访问双字的地址，边界电路都检测该条件并使定时电路仅生成访问第一字位置所需的定时信号。

公开(公告)号：EP0055128A2

公开(公告)日：1982-06-30

申请号：EP81306043.1

申请日：1981-12-22

申请人： Honeywell Bull Inc.

发明人： Tague, Steven A. ,  Negi, Virendra S.

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F5/00

CPC分类号： G06F9/226

摘要： A data processing system includes a commercial instruction processor for executing decimal alphanumeric instructions uses read only memories in the alignment of the operands. The characteristics of the operands, string or packed decimal as well as the length and position of the most significant decimal digit in a main memory word are specified by data descriptors. The read only memories are responsive to the data descriptor information as well as the instruction being executed to generate signals which specify whether the direction words are read from main memory is high order word first or low order word first, the number of double words in the operand, and the location of the least or most significant decimal digit within the word as stored in registers of the commercial instruction processor. A register coupled to an arithmetic logic unit stores double words of the operands wich are written into the register as double words, bytes or decimal digits. A multiplexer is responsive to control store signals and descriptor signals for generating write control signals which are applied to a read only memory, whose output write signals select the decimal digit, byte or double word positions of the register for writing. Another read only memory generates signals indicating next decimal digit position to be processed.

摘要翻译： 一种数据处理系统包括商业指令处理器，用于执行十进制字母数字指令，在操作数的对齐中使用只读存储器。 通过数据描述符指定操作数，字符串或压缩十进制数的特征以及主存储字中最高有效小数位的长度和位置。 只读存储器响应于数据描述符信息以及正在执行的指令以产生信号，该信号指定从主存储器读取的方向字是高位字首先还是低位字首先是双字的数目 操作数，以及存储在商业指令处理器的寄存器中的字内最小或最高有效位的位置。 耦合到算术逻辑单元的寄存器存储将作为双字，字节或十进制数字写入寄存器的操作数的双字。 多路复用器响应于控制存储信号和描述符信号以产生写入控制信号，该写入控制信号被施加到只读存储器，该只读存储器的输出写入信号选择用于写入的寄存器的十进制数字，字节或双字位置。 另一只读存储器产生指示要处理的下一个十进制数字位置的信号。

公开(公告)号：EP0264740A3

公开(公告)日：1989-11-15

申请号：EP87114768.2

申请日：1987-10-09

申请人： Honeywell Bull Inc.

发明人： Izbicki, Kenneth J. ,  Woods, William E. ,  Lemay, Richard A. ,  Tague, Steven A.

IPC分类号： G06F13/40 ,  G06F13/42

CPC分类号： G06F13/4217

摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.

公开(公告)号：EP0080901B1

公开(公告)日：1989-08-09

申请号：EP82306383.9

申请日：1982-12-01

申请人： Honeywell Bull Inc.

发明人： Woods, William E. ,  Stanley, Philip E.

IPC分类号： G06F9/30 ,  G06F9/26

CPC分类号： G06F9/30192 ,  G06F9/26 ,  G06F9/268

公开(公告)号：EP0087266B1

公开(公告)日：1989-08-02

申请号：EP83300778.4

申请日：1983-02-16

申请人： Honeywell Bull Inc.

发明人： Brown, Richard P. ,  Lemay, Richard A. ,  Steiner, Lewis G. ,  Woods, William E.

IPC分类号： G06F13/00

CPC分类号： G06F13/18

公开(公告)号：EP0288000A2

公开(公告)日：1988-10-26

申请号：EP88106207.9

申请日：1988-04-19

申请人： Honeywell Bull Inc.

发明人： Henneberg, Helmut H. ,  Dillon, Richard R.

IPC分类号： H05K7/20 ,  G06F1/00

CPC分类号： G06F1/20 ,  G06F1/181

摘要： The electronic equipment of a computer system including electronic cards, power supplies, peripheral units, cooling units and internal and external cables are compactly packaged within a small enclosure in a way which permits sufficient airflow from front to rear of the enclosure. The enclosure includes a pair of rail members located at the rear which have a plurality of mounting positions for attaching a corresponding number of modular shelf members which are angled to permit the flow of air through established airflow paths. The rail and shelf members collectively form a bulkhead structure. The rail members are offset from the sides of the frame so as to form vertical channels on each side. The channels are used for retaining external cables which plug into connectors mounted on the shelf members and are distributed so as not to interfere with airflow.

摘要翻译： 包括电子卡，电源，外围单元，冷却单元以及内部和外部电缆在内的计算机系统的电子设备以小的外壳紧密地封装，从而允许从外壳的前部到后部具有足够的气流。 外壳包括位于后部的一对轨道构件，其具有多个安装位置，用于附接相应数量的模块化搁架构件，所述多个模块化搁架构件成角度以允许空气流经已建立的气流路径。 轨道和搁板部件共同形成隔板结构。 轨道构件从框架的侧面偏移，以便在每一侧上形成垂直通道。 这些通道用于固定外部电缆，将外部电缆插入到安装在搁板构件上的连接器中，并分布成不会干扰气流。