公开(公告)号：EP1912223A1

公开(公告)日：2008-04-16

申请号：EP07011551.4

申请日：2003-02-26

申请人： SanDisk Corporation

发明人： Li, Yan ,  Chen, Jian

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/28 ,  G11C16/3418

摘要： The present invention presents a non-volatile memory having a plurality of erase units or blocks, where each block is divided into a plurality of parts sharing the same word lines to save on the row decoder area, but which can be read or programmed independently. An exemplary embodiment is a Flash EEPROM memory with a NAND architecture that has blocks composed of a left half and a right half, where each part will accommodate one or more standard page (data transfer unit) sizes of 512 bytes of data. In the exemplary embodiment, the left and right portions of a block each have separate source lines, and separate sets of source and drain select lines. During the programming or reading of the left side, as an example, the right side can be biased to produce channel boosting to reduce data disturbs. In an alternate set of embodiments, the parts can have separate well structures.

摘要翻译： 本发明提出具有擦除单元或块，其中每个块被划分为部分共享相同的字线，以节省行译码器区域的多个A多个A的非易失性存储器，但是其可被读取或编程unabhängig。 有助于示例性实施例是具有NAND结构的快闪EEPROM存储器确实具有左和右一半，其中每个部分将容纳一个或多个标准页（数据传输单元）的512个字节的数据的大小构成的块。 在该示例性，实施例的左和右的块的每个部分具有单独的源极线和源极的独立套和漏极选择线。 在编程或左侧的读出，如实施例中，右侧可以被偏置以产生沟道升压以减少数据会干扰。 在一个备选组实施方案中，该部分可以有单独的阱结构。

公开(公告)号：EP1665284B1

公开(公告)日：2008-02-27

申请号：EP04784312.3

申请日：2004-09-16

申请人： SanDisk Corporation

发明人： KHALID, Shahzad ,  LI, Yan ,  CERNEA, Raul-Adrian ,  MOFIDI, Mehrdad

IPC分类号： G11C16/34 ,  G11C16/04

CPC分类号： G11C16/3468 ,  G11C16/0483

摘要： When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

公开(公告)号：EP1652189B8

公开(公告)日：2008-02-13

申请号：EP04779231.2

申请日：2004-07-27

申请人： SanDisk Corporation

发明人： CERNEA, Raul-Adrian

IPC分类号： G11C5/14 ,  H02M3/07

CPC分类号： G11C5/145 ,  H02M3/073

摘要： A first charge pump includes a collection of voltage adder stages. The first voltage adder stage receives an input voltage VCC and in response to a clock signal provides a first voltage signal alternating between 2*VCC and VCC. The Nth voltage adder stage receives an input voltage VCC and a first voltage signal from the preceding stage, and provides a second voltage signal alternating between N*VCC and VCC. The capacitors included within each adder stage are required to sustain a maximum voltage of VCC. In an alternate embodiment the first charge pump may be combined with one or more voltage doubler stages to produce even higher output voltages.

公开(公告)号：EP1466331B1

公开(公告)日：2008-02-13

申请号：EP02806618.1

申请日：2002-12-16

申请人： SanDisk Corporation

发明人： MOKHLESI, Nima ,  GUTERMAN, Daniel, C. ,  GONGWER, Geoffrey, S.

IPC分类号： G11C16/26

CPC分类号： G11C11/5642 ,  G11C16/0458 ,  G11C16/26

摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

公开(公告)号：EP1374243B1

公开(公告)日：2008-02-13

申请号：EP02717750.0

申请日：2002-03-29

申请人： SanDisk Corporation

发明人： GONGWER, Geoffrey, S. ,  KHALID, Shahzad

IPC分类号： G11C5/14 ,  G11C8/08 ,  G11C16/08 ,  H03K17/30

CPC分类号： G11C5/145 ,  G11C8/08

摘要： Driver (100) and method are provided for driving capacitive load (120) that achieve an improved response time without increasing power consumption of the driver. Driver (100) has load buffer (105) with an input (110) for receiving an input voltage (VIN), and an output (115) for coupling an output voltage (VOUT) to load (120). VOUT is driven between a first voltage level (V1) and a second voltage level (V2) in response to changes in VIN. Driver (100) also has reserve circuit (125) with capacitor (130), reserve buffer (135), switch (140) for coupling the capacitor to capacitive load (120) and controller (145) for operating the switch. Reserve buffer (135) has an input (150) for receiving an input voltage (VRES_IN), and an output (155) for coupling an output voltage (VRES_OUT) to capacitor (130) to charge the capacitor. Controller (145) is configured to operate switch (140) to couple capacitor (130) to capacitive load (120) when VOUT is being driven between V1 and V2.

公开(公告)号：EP1309919B1

公开(公告)日：2008-02-13

申请号：EP01965945.7

申请日：2001-08-14

申请人： SanDisk Corporation

发明人： CEDAR, Yoram ,  HOLTZMAN, Micky ,  PINTO, Yosi

IPC分类号： G06F13/38

CPC分类号： G06F13/1694 ,  G06F12/0653 ,  G06F12/0661 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4239 ,  G06F2212/2022 ,  G06F2213/0052

摘要： Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines.

公开(公告)号：EP1884103A2

公开(公告)日：2008-02-06

申请号：EP06770988.1

申请日：2006-05-23

申请人： Sandisk Corporation

发明人： JOGAND-COULOMB, Fabrice ,  QAWAMI, Bahman ,  SABET-SHARGHI, Farshid

IPC分类号： H04L29/06

CPC分类号： H04L63/10 ,  G06F21/10 ,  G06F2221/2135 ,  G06Q20/10 ,  H04L2463/101 ,  H04N21/4788 ,  H04N21/632

摘要： A method and system for conducting a transaction involving digital content is provided. The system includes, a first user of a first mobile device connected to a network; a second user of a second mobile device connected to the network; a MNO that is functionally coupled to the first mobile device and the second mobile device and to a digital content provider and a rights issuing authority. The MNO receives a request for digital content from the first user, searches for the requested digital content and if the second user has the requested digital content, then the MNO obtains any rights to re-distribute/access the requested digital content; and the second user, the digital content provider and the MNO are compensated for distributing the requested digital content from the second mobile device to the first mobile device.

公开(公告)号：EP1881504A2

公开(公告)日：2008-01-23

申请号：EP07021800.3

申请日：2005-01-10

申请人： SanDisk Corporation

发明人： Hemink, Gertjan ,  Fong, Yupin

IPC分类号： G11C16/34 ,  G11C11/56

CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621

摘要： One or more programming operations are performed on a set of non-volatile storage elements. For example, the programming operations may include applying a set of programming pulses. A verify process is performed to determine which of the non-volatile storage elements have reached an intermediate verify threshold but have not reached a final verify threshold. One additional programming operation at a reduced level is performed for the non-volatile storage elements that have reached the intermediate verify threshold but have not reached the final verify threshold, and those non-volatile storage elements are then inhibited from further programming. Non-volatile storage elements that have not reached the intermediate verify threshold continue programming. Non-volatile storage elements that reach the final verify threshold are inhibited from programming.

摘要翻译： 对一组非易失性存储元件执行一个或多个编程操作。 例如，编程操作可以包括应用一组编程脉冲。 执行验证处理以确定哪些非易失性存储元件已经达到中间验证阈值但尚未达到最终验证阈值。 对于已经达到中间验证阈值但尚未达到最终验证阈值的非易失性存储元件执行降级的一个附加编程操作，然后禁止那些非易失性存储元件进一步编程。 尚未达到中间验证阈值的非易失性存储元件继续编程。 达到最终验证阈值的非易失性存储元件被禁止编程。

公开(公告)号：EP1880419A1

公开(公告)日：2008-01-23

申请号：EP06752522.0

申请日：2006-05-11

申请人： SanDisk Corporation

发明人： TAKIAR, Hem ,  UPADHYAYULA, Suresh

IPC分类号： H01L25/16 ,  G06K19/077

CPC分类号： H01L24/97 ,  H01L25/167 ,  H01L2224/48227 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  Y10T29/49002 ,  H01L2924/00

摘要： Methods of forming integrated circuit packages having an LED molded into the package, and the integrated circuit package formed thereby. An integrated circuit including one or more semiconductor die, passive components and an LED may be assembled on a panel. The one or more semiconductor die, passive components and LED may all then be encapsulated in a molding compound, and the integrated circuits then singularized to form individual integrated circuit packages. The integrated circuits are cut from the panel so that a portion of the lens of the LED is severed during the singularization process, and an end of the lens remaining within the package lies flush with an edge of the package to emit light outside of the package.

公开(公告)号：EP1769508B1

公开(公告)日：2007-12-26

申请号：EP05770198.9

申请日：2005-07-08

申请人： SanDisk Corporation

发明人： MOOGAT, Farookh ,  LI, Yan ,  MAK, Alexander K.

IPC分类号： G11C16/10 ,  G11C16/30

CPC分类号： G11C16/10 ,  G11C16/30

摘要： In a non-volatile memory system (20), when it is discovered that the voltage pump pulse provided by a charge pump (32) for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

摘要翻译： 在非易失性存储器系统（20）中，当发现由用于编程存储器单元的电荷泵（32）提供的电压泵脉冲与参考电压不匹配时，电压泵脉冲的编程时间段是 调整为在编程周期结束前保持基本不变的值。 以这种方式，编程脉冲的有效编程时间周期中的波动被阻止用于编程周期的其余部分，使得阈值电压分布的扩展不会发生或将减少。 此功能允许为编程脉冲指定一个较短的编程时间段以提高性能，同时允许电荷泵在其导致其缓慢和/或较弱的条件下运行时增加编程时间段的灵活性。