公开(公告)号：EP1929318A1

公开(公告)日：2008-06-11

申请号：EP06804150.8

申请日：2006-09-26

申请人： Teradyne, Inc.

发明人： SARTSCHEV, Ronald, A.

IPC分类号： G01R31/319

CPC分类号： G01R31/31924

摘要： Circuitry for driving a pin of a device includes a first circuit path terminating in a first impedance, a second circuit path terminating in a second impedance, where the second impedance is less than the first impedance, and a selection circuit to control operation of the second circuit path. When the second circuit path is not configured for operation, the first circuit path is configured to output one of plural first voltage signals. When the second circuit path is in configured for operation, the second circuit path is configured to output a second voltage signal. The second voltage signal is greater than the plural first voltage signals.

公开(公告)号：EP1904865A1

公开(公告)日：2008-04-02

申请号：EP06771064.0

申请日：2006-05-23

申请人： Teradyne, Inc.

发明人： SARTSCHEV, Ronald A.

IPC分类号： G01R31/319

CPC分类号： G01R31/31924 ,  G01R31/319

摘要： Circuitry for driving a pin includes a first resistive circuit connected to the pin, a first transistor circuit to connect the first resistive circuit to a logic level voltage in response to a trigger voltage, the first transistor circuit and the first resistive circuit together defining a termination impedance, and a driver circuit to apply the trigger voltage to the first transistor circuit. The driver circuit includes counterparts to the first resistive circuit and the first transistor circuit. The counterparts define a counterpart impedance that is controlled to control the trigger voltage and thereby control the termination impedance.

公开(公告)号：EP1470432B1

公开(公告)日：2007-12-05

申请号：EP03707580.1

申请日：2003-01-29

申请人： FormFactor, Inc.

发明人： ELDRIDGE, Benjamin, N. ,  MILLER, Charles, A.

IPC分类号： G01R31/316 ,  G01R31/319

CPC分类号： G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

摘要： A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

公开(公告)号：EP1832888A1

公开(公告)日：2007-09-12

申请号：EP06004879.0

申请日：2006-03-09

申请人： Teradyne, Inc.

发明人： Balke, Christian c/o Teradyne GmbH ,  Da Costa, Cristo c/o Teradyne GmbH

IPC分类号： G01R31/319

CPC分类号： G01R31/31924

摘要： A V/I-source, comprising a diode quad or an equivalent circuit having first through fourth nodes, a first current source connected to a 1 st node of said diode quad, a second current source connected to a 2 nd node of said diode quad opposite said first node, an op-amp having its output connected to a 3 rd node of said diode quad and its non-inverting input being connected to a voltage source a feedback line arranged between a 4 th node of said diode quad opposite said 3 rd node and said inverting input of said op-amp. Furthermore, A test system for testing electronic devices, incorporating such a V/I-source and a method for providing a V/I-source and for testing an electronic device are provided.

摘要翻译： AV / I源，包括具有第一至第四节点的二极管四极管或等效电路，连接到所述二极管四极管的第一节点的第一电流源，连接到所述二极管四极相对的第二节点的第二电流源 所述第一节点，其输出端连接到所述二极管四极管的第三节点的运算放大器，其非反相输入端连接到电压源，反馈线路布置在与所述二极管四极相对的所述二极管四极管的第四节点之间 节点和所述运算放大器的所述反相输入。 此外，提供了一种用于测试电子设备的测试系统，包括这样的V / I源和用于提供V / I源和测试电子设备的方法。

公开(公告)号：EP1157279B1

公开(公告)日：2007-04-18

申请号：EP00914494.0

申请日：2000-02-03

申请人： Teradyne, Inc.

发明人： WALKER, Ernest, P. ,  SARTSCHEV, Ronald, A. ,  RYAN, Allan, M., Jr. ,  BLOM, Eric, D.

IPC分类号： G01R31/319

CPC分类号： G01R31/31908 ,  G01R31/3191 ,  G01R31/31924

摘要： Pin slice circuitry used in automatic test equipment is disclosed. The pin slice circuitry includes a portion implemented using CMOS technology and a portion implemented using bipolar technology. The CMOS portion includes a plurality of timing generator circuits, digital sigma delta modulator circuitry used to generate digital bit streams representative of analog reference levels, and programmable digital signal processing circuitry. The bipolar portion includes driver/receiver channels, a parametric measurement unit, and decoder circuitry, which produces the analog reference levels from the digital bit streams generated by the modulator circuitry. The analog reference levels are used by the driver/receiver channels and the parametric measurement unit; and, the digital signal processing circuitry is used to monitor and control levels produced by the parametric measurement unit. The disclosed pin slice circuitry has the advantages of reduced size and cost as compared with conventional pin slice circuitry.

公开(公告)号：EP1722247A2

公开(公告)日：2006-11-15

申请号：EP06015765.8

申请日：2003-07-09

申请人： FormFactor, Inc.

发明人： Miller, Charles A.

IPC分类号： G01R31/319 ,  G06F11/273

CPC分类号： G01R31/3191 ,  G01R31/31723 ,  G01R31/31908 ,  G01R31/31924

摘要： An electronic device tester channel transmits a single test signal to multiple terminals of electronic devices under test (DUTs) through a set of isolation resistors. The tester channel employs feedback to automatically adjust the test signal voltage to compensate for affects of faults at any of the DUT terminals to prevent the faults from substantially affecting the test signal voltage.

摘要翻译： 电子设备测试仪通道通过一组隔离电阻将单个测试信号发送到被测电子设备（DUT）的多个终端。 测试仪通道采用反馈自动调整测试信号电压，以补偿任何DUT端子故障的影响，以防止故障基本上影响测试信号电压。

公开(公告)号：EP1618397A2

公开(公告)日：2006-01-25

申请号：EP04750816.3

申请日：2004-04-27

申请人： TERADYNE, INC.

发明人： LEIP, David, G.

IPC分类号： G01R31/319 ,  G01R31/3193 ,  G01R19/10 ,  G01R19/165

CPC分类号： G01R19/10 ,  G01R19/16576 ,  G01R31/31924 ,  G01R31/3193

摘要： A measurement circuit for measuring input voltages in an automatic test system includes a pedestal source, a differential amplifier, and a feedback amplifier. The differential amplifier measures a 'residue,' i.e., a difference between an input signal and a pedestal signal from the pedestal source, which is programmed to equal an expected input voltage. The feedback amplifier boosts the residue before it is presented to the differential amplifier, and thus allows the differential amplifier to be operated at lower gain than is typically used in conventional topologies. Consequently, the effect of the errors in the differential amplifier are reduced.

公开(公告)号：EP1095286B1

公开(公告)日：2005-08-03

申请号：EP00928934.9

申请日：2000-05-08

申请人： TERADYNE, INC.

发明人： BREGER, Peter

IPC分类号： G01R31/28 ,  H03K5/12

CPC分类号： G01R31/31924

摘要： A driver for applying a deterministic waveform along a lossy transmission path to a device-under-test is disclosed. The driver includes a signal generator for producing a substantially square-wave signal at an output node and an injector coupled to the output node for modifying the square-wave signal to pre-compensate for expected losses along the lossy path.

公开(公告)号：EP1070260B1

公开(公告)日：2005-07-20

申请号：EP00907472.5

申请日：2000-01-13

申请人： Koninklijke Philips Electronics N.V.

发明人： JANSSEN, Petrus, J., M. ,  HART, Cornelis, M.

IPC分类号： G01R31/30 ,  G01R31/319

CPC分类号： G01R31/3191 ,  G01R31/3004 ,  G01R31/31905 ,  G01R31/31924

公开(公告)号：EP1166137A4

公开(公告)日：2004-12-29

申请号：EP00916245

申请日：2000-03-08

申请人： CREDENCE SYSTEMS CORP

发明人： DINTEMAN BRYAN J

IPC分类号： G01R31/316 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/319 ,  G06F11/00 ,  G06F11/22 ,  H04B1/74

CPC分类号： G01R31/31924

摘要： An integrated circuit (IC) tester includes a set of dual-purpose digital/analog channels. Each tester channel includes a driver capable of supplying either a digital or analog test signal input to an IC terminal and a receiver for digitizing and processing either an analog or digital IC output signal appearing at the DUT terminal to produce results data representing the behavior of that IC output signal during a test. A test is organized into a succession of test cycles, and before each test cycle a pattern generator (30) within each channel produces data for controlling the behavior of the driver (34) and receiver (38) during the test cycle. The control data controls whether the driver (34) is to produce an analog or a digital test signal, controls a magnitude or logic level to which the test signal is to be driven during the test cycle, and controls a time during the test cycle of any test signal state or magnitude changes. The control data also indicates how and when the receiver (38) digitizes and processes an IC output signal during the test cycle.