公开(公告)号：EP1070385A4

公开(公告)日：2004-11-17

申请号：EP99918465

申请日：1999-04-02

申请人： CREDENCE SYSTEMS CORP

发明人： DINTEMAN BRYAN J ,  WOHLFARTH PAUL DANA

IPC分类号： G01R31/28 ,  G01R31/319 ,  H03B1/00 ,  G01R31/316

CPC分类号： G01R31/31924 ,  G01R31/2839

摘要： A drive circuit for an integrated circuit tester (10) operates in either a drive mode or in a termination mode.

公开(公告)号：EP0653072A4

公开(公告)日：1995-11-22

申请号：EP93918395

申请日：1993-07-26

申请人： CREDENCE SYSTEMS CORP

发明人： DINTEMAN BRYAN J

IPC分类号： G01R31/28 ,  G01R31/319

CPC分类号： G01R31/31922 ,  G01R31/2834

摘要： Apparatus for testing an integrated circuit device (DUT) having an input port and an output port comprises multiple state devices (10-16) each having multiple states that occur in a predetermined sequence and an output port at which it provides an event signal. A first of the state device is an emitting device (10) that emits an event marker signal at a predetermined time in advance of entering a predefined state, a second of the state devices is a receiving device (11) that responds to receipt of an event marker signal, at least one of the state devices (11) has its output port connected to the input port of the DUT, and at least one of the state devices is a measurement device (13) connected to the output port of the DUT. An interconnection matrix (30) is connected to each state device and allows each state device to communicate an event marker signal to each other.

摘要翻译： 用于测试具有输入端口和输出端口的集成电路器件（DUT）的装置包括多个状态装置（10-16），每个状态装置具有以预定顺序发生的多个状态和提供事件信号的输出端口。 状态设备的第一个是发射设备（10），其在进入预定义状态之前的预定时间发射事件标记信号，第二个状态设备是接收设备（11），其响应于接收到 事件标记信号，至少一个状态装置（11）的输出端口连接到DUT的输入端口，并且至少一个状态装置是连接到DUT的输出端口的测量装置（13） 。 互连矩阵（30）连接到每个状态设备并且允许每个状态设备将事件标记信号彼此通信。

公开(公告)号：EP1147470A4

公开(公告)日：2004-12-29

申请号：EP00904189

申请日：2000-01-03

申请人： CREDENCE SYSTEMS CORP

发明人： DINTEMAN BRYAN J ,  BEDELL DANIEL J

IPC分类号： G01R31/28 ,  G01R31/316 ,  G01R31/3167 ,  G01R31/319 ,  G06F11/22 ,  G06F11/263

CPC分类号： G01R31/31907 ,  G01R31/3167 ,  G01R31/31917 ,  G01R31/31922

摘要： An integrated circuit tester (10) includes a set of digital (14(1)-14(N)) and analog channels (16(1)-16(M)), each of which may be programmed to carry out a sequence of test activities at pins of an integrated circuit under test (12). The channels are interconnected by a trigger bus (24), and each channel may be programmed to respond to a detected event during a test by transmitting a particular trigger code to every other channel via the trigger bus (24). Each channel may also be programmed to respond to a particular trigger code arriving on the trigger bus (24) by branching its sequence of test activities. Thus any channel detecting an event during a test can signal all other channels to immediately terminate a current sequence of test activities and branch to another set of test activities.

公开(公告)号：EP1095287A4

公开(公告)日：2004-12-29

申请号：EP99927320

申请日：1999-06-07

申请人： CREDENCE SYSTEMS CORP

发明人： SLIZYNSKI ROMAN A ,  DINTEMAN BRYAN J

IPC分类号： G01R31/28 ,  G01R31/316 ,  G01R31/3193

CPC分类号： G01R31/31935 ,  G01R31/316

摘要： A general purpose integrated circuit (I) tester (10) includes a set of channels (18), one for each input or output pin of an I device under test (DUT) (12). Each channel (18) is programmed by a host computer (22) to either supply a test signal to a DUT I/O pin (14, 16) or sample a DUT output signal appearing at the I/O pin (14, 16) and produce sample data representing its magnitude or logic state. The tester (10) also includes an amorphous logic circuit (ALC) (30) having a set of input and output terminals (28) and a programmable logic circuit interconnecting the input and output terminals. Some of the ALC input and output terminals (28) receive the sample data produced by each channel (18) and other ALC terminals send control signals directly to each channel (18). Other ALC terminals transmit data to the host computer (22).

公开(公告)号：EP1166137A4

公开(公告)日：2004-12-29

申请号：EP00916245

申请日：2000-03-08

申请人： CREDENCE SYSTEMS CORP

发明人： DINTEMAN BRYAN J

IPC分类号： G01R31/316 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/319 ,  G06F11/00 ,  G06F11/22 ,  H04B1/74

CPC分类号： G01R31/31924

摘要： An integrated circuit (IC) tester includes a set of dual-purpose digital/analog channels. Each tester channel includes a driver capable of supplying either a digital or analog test signal input to an IC terminal and a receiver for digitizing and processing either an analog or digital IC output signal appearing at the DUT terminal to produce results data representing the behavior of that IC output signal during a test. A test is organized into a succession of test cycles, and before each test cycle a pattern generator (30) within each channel produces data for controlling the behavior of the driver (34) and receiver (38) during the test cycle. The control data controls whether the driver (34) is to produce an analog or a digital test signal, controls a magnitude or logic level to which the test signal is to be driven during the test cycle, and controls a time during the test cycle of any test signal state or magnitude changes. The control data also indicates how and when the receiver (38) digitizes and processes an IC output signal during the test cycle.

公开(公告)号：EP1050053A4

公开(公告)日：2004-10-20

申请号：EP99903388

申请日：1999-01-26

申请人： CREDENCE SYSTEMS CORP

发明人： DINTEMAN BRYAN J

IPC分类号： G01R31/28 ,  G01R31/319 ,  G11C29/56 ,  G11C29/00

CPC分类号： G01R31/31919 ,  G01R31/31922

摘要： A drive circuit for an integrated circuit tester produces an output test signal in response to an input sequence of vector data values, wherein each vector data value references a test signal state and a time at which the test signal is to change to the referenced state. The drive circuit includes decoding and timing circuits for producing an indicating signal (D) of the state referenced by each incoming vector data value and a timing signal (TD) having a pulse occurring at the time referenced by the incoming vector data value. An event phase modulator within the drive circuit stores a control bit indicating the state of the indicating signal in response to each pulse of the timing signal. The event phase modulator waits for a variable amount of time after storing each control bit and then forwards the control bit to the input of a driver producing the test signal. The driver sets the test signal state in accordance with the state of the control bit. The delay between the time the event phase modulator stores a control bit and forwards it to the driver is a function of time determined by input programming data. Thus the event phase modulator phase modulates the test signal in a manner determined by its input programming data.

摘要翻译： 用于集成电路测试器的驱动电路响应于矢量数据值的输入序列产生输出测试信号，其中每个矢量数据值引用测试信号状态和测试信号将改变为参考状态的时间。 驱动电路包括用于产生由每个输入矢量数据值引用的状态的指示信号（D）的解码和定时电路以及在由输入矢量数据值引用的时刻出现的脉冲的定时信号（TD）。 驱动电路内的事件相位调制器存储响应于定时信号的每个脉冲指示指示信号的状态的控制位。 事件相位调制器在存储每个控制位之后等待可变量的时间，然后将控制位转发到产生测试信号的驱动器的输入端。 驱动器根据控制位的状态设置测试信号状态。 事件相位调制器存储控制位并将其转发给驱动器的时间之间的延迟是由输入编程数据确定的时间的函数。 因此，事件相位调制器以其输入编程数据确定的方式调制测试信号。

公开(公告)号：EP1080532A4

公开(公告)日：2004-03-31

申请号：EP99919942

申请日：1999-04-20

申请人： CREDENCE SYSTEMS CORP

发明人： SLIZYNSKI ROMAN A ,  REYNOLDS DAVID D ,  DINTEMAN BRYAN J ,  BEDELL DANIEL J

IPC分类号： H03M1/12 ,  H03M1/00

CPC分类号： H03M1/1245

摘要： A digitizer can be programmed to digitize an ANALOG signal with a complex frequency pattern determined in response to a set of trigger signals (TRIGIN, TRIGOUT). The digitizer includes an addressable packet memory (18) storing a set of data packets and produces one of its stored data packets as output when addressed. The output data packet includes both PERIOD and MODE data fields. The digitizer also includes an analog to digital converter (12) for digitizing an ANALOG signal at the frequency controlled by the Period data output of the packet memory. The MODE data output of the packet memory tells a trigger logic circuit (20) how to choose a next packet memory address and selects one of the trigger signals to tell the trigger logic circuit when to change the packet memory address so as to alter the digitizing frequency.

摘要翻译： 可以对数字化仪进行编程，以根据一组触发信号（TRIGIN，TRIGOUT）确定的复杂频率模式对ANALOG信号进行数字化。 数字化器包括存储一组数据分组的可寻址分组存储器（18），并在寻址时产生其存储的数据分组之一作为输出。 输出数据包包括PERIOD和MODE数据字段。 数字转换器还包括一个模数转换器（12），用于以由分组存储器的周期数据输出控制的频率对ANALOG信号进行数字化。 分组存储器的MODE数据输出告诉触发逻辑电路（20）如何选择下一个分组存储器地址，并选择其中一个触发信号告诉触发逻辑电路何时改变分组存储器地址以改变数字化 频率。