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公开(公告)号：EP0744051A4
公开(公告)日：1997-06-04
申请号：EP95910277
申请日：1995-02-09
发明人： KIKINIS DAN
CPC分类号： G06F9/4411 , G06F13/4004 , G06F13/4022
摘要： An I/O control system (19) for a general-purpose computer (13) having multiple bus branches (21) separated by routing circuitry (43, 44) prepares a digital map (48, 53) of I/O device locations on the bus branches, and copies versions of the maps to registers in the routing circuitry (213) on startup and reset (211). The routing maps provide immediate routing information for I/O requests issued by one or more CPUs (40, 41, 42) in a system, allowing therouting circuitry between bus branches to immediately route requests to the proper device with a minimum of wait states. In one aspect I/O devices are polled (205) for location at startup and reset (201), and in another aspect, a universal map protocol (207) is a part of the BIOS or storage accessible by the BIOS, making a system self-configuring and providing the necessary information for the mapping for the routing circuitry.
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72.发明公开Data processor with controlled burst memory accesses and method therefor 失效Datenprozessor mit gesteuertem Stoss-Speicherzugriff und Vorrichtungdafür
公开(公告)号：EP0700003A2
公开(公告)日：1996-03-06
申请号：EP95113370.1
申请日：1995-08-25
申请人： MOTOROLA, INC.
CPC分类号： G06F12/1441 , G06F13/28 , G06F13/4004 , G06F13/4018 , G06F13/4243
摘要： A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).
摘要翻译： 数据处理器（21）包括响应于两个内部总线主设备（30,34）执行固定或可变突发存取的外部总线接口电路（33）。 数据处理器（21）激活外部控制信号以指示突发存取是固定的还是可变突发存取。 数据处理器（21）通过向外部总线接口电路（33）提供端口尺寸信号来指示所访问的存储器区域的端口大小。 如果所访问的位置对应于存储器（24），外部总线接口电路（33）响应于端口大小信号将突发周期分解成外部总线（22,23）上的两个或更多突发周期， 与内部总线（31）不同的端口大小。
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公开(公告)号：EP0610426A1
公开(公告)日：1994-08-17
申请号：EP92924152.0
申请日：1992-10-29
CPC分类号： G06F13/4004 , H03K19/017581 , H03K19/01759
摘要： Un tampon bidirectionnel (94) comprend des premier (100) et second (102) tampons unidirectionnels connectés pour retransmettre des signaux dans des sens opposés entre des premier et second bus. Lorsqu'un circuit d'attaque de bus externe fait baisser la tension du premier bus, le premier tampon unidirectionnel (100) fait baisser celle du second bus et génère un signal empêchant le second tampon unidirectionnel d'attaquer activement le premier bus. Lorsque le circuit d'attaque de bus externe permet au premier bus de revenir au niveau logique élevé, le premier tampon unidirectionnel (100) fournit temporairement un courant de charge élevé au second bus afin de faire monter rapidement sa tension. De même, lorsqu'un circuit d'attaque de bus externe fait baisser la tension du second bus, le second tampon unidirectionnel (102) fait baisser celle du premier bus et génère un signal empêchant le premier tampon unidirectionnel d'attaquer activement le second bus. Lorsque le circuit d'attaque de bus externe permet au second bus de revenir au niveau logique élevé, le second tampon (102) fournit temporairement un courant de charge élevé au premier bus afin de faire monter rapidement sa tension.
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74.发明公开Mechanism for controlling the resources of a distributed information processing system 失效Vorrichtung zum Steuern von Betriebsmitteln eines verteilten Informationsverarbeitungssystems。
公开(公告)号：EP0505651A1
公开(公告)日：1992-09-30
申请号：EP91480051.1
申请日：1991-03-29
发明人： Brezzo, Bernard , Calvignac, Jean-Louis , Munier, Jean-Marie , Naudin, Bernard, "les Provencales" , Robbe, Jean-Claude
CPC分类号： G06F13/4004 , G06F13/385 , G06F13/4031
摘要： A data processing system includes data processing adapters (2) for controlling the data transfers between end systems (1) and a memory through contention type busses (7 and 11) and a control processor connected to the system bus (7) for through a coupler (8) for controlling the physical resources such as registers or memories of the whole data processing system. A control operation is initiated by the control processor which presents on its processor bus (14) a control operation to be executed in a destination unit which can be the coupler, a selected data processing adapter or a selected end system. Each unit is provided with a control operation interface dedicated to the processing of the control operation or its forwarding toward the destination unit and the preparation of a response to the control operation in the destination unit and the propagation of the response toward the coupler, so as to minimize the bus occupancy times.
摘要翻译： 数据处理系统包括用于通过竞争型总线（7和11）控制终端系统（1）和存储器之间的数据传输的数据处理适配器（2）和连接到系统总线（7）的控制处理器，用于通过耦合器 （8），用于控制诸如整个数据处理系统的寄存器或存储器的物理资源。 由控制处理器启动控制操作，控制处理器在其处理器总线（14）上呈现要在可以是耦合器，所选数据处理适配器或选定端系统的目的地单元中执行的控制操作。 每个单元设置有专用于处理控制操作或其向目的地单元的转发的控制操作界面以及对目的地单元中的控制操作的响应的准备以及响应朝向耦合器的传播，从而 以最小化公交车的占用时间。
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公开(公告)号：EP0156542B1
公开(公告)日：1990-09-05
申请号：EP85301476.9
申请日：1985-03-04
CPC分类号： G06F13/4004 , H04L12/4625 , H04L45/742
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公开(公告)号：EP2799979B1
公开(公告)日：2017-11-22
申请号：EP12861586.1
申请日：2012-05-08
发明人： YUAN, Cissy , MAO, Erkun , WANG, Jian , TIAN, Xuehong , ZENG, Daibing , TIAN, Wanting , CHEN, Qian
IPC分类号： G06F5/06
CPC分类号： G06F13/4004 , G06F5/06 , G06F7/78 , G06F9/44505
摘要： A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency.
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公开(公告)号：EP2909730B1
公开(公告)日：2017-08-16
申请号：EP13780471.2
申请日：2013-10-09
发明人： GANASAN, Jaya Prakash Subramaniam , SCHAFFER, Mark Michael , NOONEY, Prudhvi N. , REMAKLUS, Perry, Willmann, Jr.
IPC分类号： G06F13/368
CPC分类号： G06F13/4027 , G06F1/3287 , G06F13/368 , G06F13/4004 , G06F15/17375 , Y02D10/14 , Y02D10/151
摘要： Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.
摘要翻译： 公开了基于处理器的系统混合环形总线互连以及相关设备，系统和方法。 在一个实施例中，提供了一种基于处理器的系统混合环形总线互连。 基于处理器的系统混合环形总线互连包括多个环形总线，每个环形总线具有总线宽度并且被配置为从请求者设备接收总线事务消息。 基于处理器的系统混合环型总线互连还包括耦合到环形总线的环之间路由器。 （一个或多个）环路间路由器被配置为基于请求者设备的带宽需求动态地在环形总线之间引导总线事务消息。 因此，由于更简单的切换配置，消耗的功率比交叉互连少。 此外，环之间路由器允许提供多个环形总线，其可以基于带宽需求动态地激活和去激活。 当不需要基于处理器的系统混合环形总线互连的全部带宽要求时，这提供了功率节省。
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78.发明公开SYSTEMS AND METHODS FOR MULTIPLE NETWORK ACCESS BY MOBILE COMPUTING DEVICES 审中-公开系统和方法访问多个网络通过移动计算机设备
公开(公告)号：EP3146765A1
公开(公告)日：2017-03-29
申请号：EP15726805.3
申请日：2015-05-14
CPC分类号： H04W8/183 , G06F13/4004 , H04J3/04 , H04W88/06 , H04W92/10 , Y02D10/14 , Y02D10/151 , Y10T29/49119
摘要： Systems and methods for multiple network access by mobile computing devices are disclosed. In one embodiment, a data bus is used to couple multiple baseband processor endpoints to multiple network access cards, such that each baseband processor endpoint may communicate over the data bus to any of the network access cards. In an exemplary, non-limiting embodiment, the baseband processor endpoint is a modem and the network access cards are subscriber interface module (SIM) cards or universal integrated circuit cards (UICCs). By allowing each of the baseband processor endpoints to use any of the network access cards, different networks may be used for different purposes by the mobile computing device. Further, the use of a single bus in this manner may allow for greater scalability, while also saving pin count, silicon area, board area, and power consumption within the computing device. Such savings ultimately improve the cost of the device.
摘要翻译： 用于通过移动计算设备的多个网络接入系统和方法是游离缺失盘。 在一个，实施例的数据总线用于耦合多个基带处理端点到多个网络接入卡，检查确实每个基带处理器端点可以通过数据总线进行通信，以任何的网络接入卡。 在一个示例性，非限制性实施例中，基带处理器端点是调制解调器和网络接入卡是用户接口模块（SIM）卡或通用集成电路卡（的UICC）。 通过允许每个所述基带处理端点的使用任何网络接入卡，可以由移动计算装置可以使用不同的网络用于不同的目的。 此外，以这种方式使用单一总线的可允许更大的可扩展性，所以同时节省了计算设备内的引脚数，硅面积，板面积和功耗。 搜索储蓄最终提高了设备的成本。
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公开(公告)号：EP3123345A1
公开(公告)日：2017-02-01
申请号：EP15704175.7
申请日：2015-01-29
发明人： HUANG, Xiaolong
CPC分类号： H04W8/005 , G06F13/4004 , G06Q30/0601 , H04L67/12 , H04L67/16 , H04W84/12
摘要： A wireless dockee may access a vendor-specific feature available on a peripheral device in communication with a wireless docking center. Information regarding the vendor-specific feature may be communicated by the wireless docking center to the wireless dockee both during pre-association discovery as well as via a service description that corresponds with the vendor-specific feature. The wireless dockee may use the received information to generate an access request to the peripheral device.
摘要翻译： 无线对接器可以访问与无线对接中心通信的外围设备上可用的供应商特定功能。 关于供应商特定特征的信息可以在预关联发现期间以及通过与特定于供应商的特征相对应的服务描述期间由无线对接中心传送给无线入坞者。 无线入坞者可使用所接收的信息来产生对外围装置的存取请求。
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公开(公告)号：EP3091696A1
公开(公告)日：2016-11-09
申请号：EP14877226.2
申请日：2014-06-16
发明人： WU, Tianyi
IPC分类号： H04L12/701
CPC分类号： H04L61/2592 , G06F9/455 , G06F9/45558 , G06F13/4004 , G06F2009/45595 , H04L12/4633 , H04L12/4641 , H04L41/12 , H04L45/56 , H04L45/586 , H04L45/74 , H04L45/745 , H04L49/25 , H04L49/354 , H04L61/103 , H04L61/2557 , H04L61/6022
摘要： In a method and an apparatus provided in embodiments of the present invention, a first switch receives an ARP response from an SDN controller, where the ARP response carries a MAC address of a destination gateway; the first switch acquires, according to the MAC address of the destination gateway, VTEP information corresponding to the MAC address of the destination gateway, where a router corresponding to the VTEP information is located in a first data center; and the first switch sends, according to the VTEP information, an IP packet to the router corresponding to the VTEP information, so that the router corresponding to the VTEP information sends the IP packet to a second virtual machine through a tunnel between the router and a second switch. Therefore, an SDN controller serves as a proxy, which reduces transmission bandwidth occupied by packet broadcasting; in addition, a packet passes only through a router of the first data center, which alleviates roundabout routing of the packet between data centers.
摘要翻译： 在本发明实施例提供的方法和装置中，第一交换机接收来自SDN控制器的ARP响应，所述ARP响应中携带目的网关的MAC地址; 所述第一交换机根据所述目的网关的MAC地址获取与所述目的网关的MAC地址对应的VTEP信息，所述VTEP信息对应的路由器位于第一数据中心; 所述第一交换机根据所述VTEP信息向所述VTEP信息对应的路由器发送IP报文，以使所述VTEP信息对应的路由器通过所述路由器与所述路由器之间的隧道将所述IP报文发送给第二虚拟机。 第二个开关。 因此，SDN控制器充当代理，减少了分组广播占用的传输带宽; 此外，数据包仅通过第一个数据中心的路由器，这减轻了数据中心之间数据包的迂回路由。
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