公开(公告)号：EP0920660B1

公开(公告)日：2008-09-03

申请号：EP98933715.9

申请日：1998-06-25

申请人： CP8 TECHNOLOGIES

发明人： UGON, Michel

IPC分类号： G06F21/22 ,  G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F21/556 ,  G06F21/57 ,  G06F21/755

摘要： The invention concerns a self-unpredictable microprocessor or microcomputer, comprising a processor (1), a first working memory (51), a main memory (6) containing an operation system, a main programme (P1) and a secondary programme (P2), characterised in that it further comprises: a second working memory (52); switching means enabling, during the execution of programmes, to switch the working memory function to one of its two working memories (51, 52) while preserving their contents; said switching means comprising at least a block of registers (54) for memorising the context of the programme process flow in the main memory and a switching circuit (53) for validating one of the working memories and access registers (A1-A3), (D1-D3) associated with each memory (51, 52, 6) and controlled by said switching circuit (53).

公开(公告)号：EP1820100B1

公开(公告)日：2008-08-27

申请号：EP05826687.5

申请日：2005-11-24

申请人： Koninklijke Philips Electronics N.V.

发明人： HEIJLIGERS, Marcus, J., M. ,  JUHASZ, Eleonora

IPC分类号： G06F9/46 ,  G06F9/38

CPC分类号： G06F9/461 ,  G06F8/451 ,  G06F9/4843

摘要： The present invention relates to a processor device, task scheduling method and computer program product, wherein tasks of a program routine are selectively stored in at least two memory stack mechanisms (62, 64) of different priorities based on the allocated priorities. Switching of tasks executed at at least two processor means (20, 30) is controlled by accessing the at least two memory stack mechanisms (62, 64) in response to synchronization instructions inserted to the program routine. Thereby, efficient zero-cycle task switching between prioritized tasks can be achieved.

公开(公告)号：EP0953905B1

公开(公告)日：2008-08-27

申请号：EP99303005.5

申请日：1999-04-19

申请人： Sony Corporation

发明人： Wakita, Yoshiro, Intellectual Property Dpt. ,  Murata, Seiji, Intellectual Property Dpt. ,  Gamo, Tsutomu, Intellectual Property Dpt.

IPC分类号： G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/461 ,  G06F9/5011 ,  G06F2209/5014 ,  G06F2209/507

公开(公告)号：EP1019794B1

公开(公告)日：2008-08-20

申请号：EP98941657.3

申请日：1998-09-24

申请人： Koninklijke Philips Electronics N.V.

发明人： LINDWER, Menno, Menasshe

IPC分类号： G06F1/00

CPC分类号： G06F9/30174 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3879 ,  G06F9/4484 ,  G06F9/45516 ,  G06F9/461

摘要： A preprocessor is functionally inserted between a memory and a processor core. The preprocessor fetches virtual machine instructions, like Java instructions, from the memory and from them it generates native instructions which are supplied to the processor core. In response to a special virtual instruction the preprocessor supplies a native jump to subroutine to the processor core, monitors when the processor core returns from that subroutine and then resumes supplying generated native instructions. The invention also provides for a processor which has a special instruction which calls a subroutine and causes the processor to convert a call context for virtual machine instructions to a call context for a high level language subroutine before making the call.

公开(公告)号：EP1698974A3

公开(公告)日：2008-04-16

申请号：EP06012989.7

申请日：1998-09-24

申请人： Sun Microsystems Inc.

发明人： Bak, Lars ,  Greisemer, Robert ,  Holzle, Urs

IPC分类号： G06F9/40

CPC分类号： G06F9/461 ,  G06F9/4484 ,  G06F9/45504

摘要： Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for functions written in different programming languages may be interleaved on the same execution stack. A data block on the execution stack may be utilized to traverse the execution stack around a frame by storing a stack pointer and frame pointer to a previous frame. Additionally, exceptions may be propagated, with conversion if necessary, through frames on the execution stack that are written in different programming languages.

公开(公告)号：EP1909177A2

公开(公告)日：2008-04-09

申请号：EP07253782.2

申请日：2007-09-25

申请人： Intel Corporation

发明人： Collins, Jaimison ,  Wang, Perry ,  Lint, Bernard ,  Yamada, Koichi ,  Mallick, Asit ,  Hankins, Richard ,  Chinya, Gautham

IPC分类号： G06F9/455

CPC分类号： G06F9/455 ,  G06F9/461

摘要： Embodiments described herein disclose a system for enabling emulation of a MIMD ISA extension which supports user-level sequencer management and control, and a set of privileged code executed by both operating system managed sequencers and application managed sequencers, including different sets of persistent per-CPU and per-thread data. In one embodiment, a lightweight code layer executes beneath the operating system. This code layer is invoked in response to particular monitored events, such as the need for communication between an operating system managed sequencer and an application managed sequencer. Control is transferred to this code layer, for execution of special operations, after which control returns back to originally executing code. The code layer is normally dormant and can be invoked at any time when either a user application or the operating system is executing.

摘要翻译： 本文描述的实施例公开了一种用于实现支持用户级定序器管理和控制的MIMD ISA扩展的仿真的系统，以及由操作系统管理的定序器和应用管理的顺控程序执行的一组特权代码，包括不同的持续性每个CPU 和每线程数据。 在一个实施例中，在操作系统之下执行轻量级代码层。 响应于特定的监视事件（例如操作系统管理定序器和应用程序管理的定序器之间的通信的需要）来调用该代码层。 控制转移到该代码层，用于执行特殊操作，之后控制返回到原始执行的代码。 代码层通常处于休眠状态，可以在用户应用程序或操作系统正在执行时随时调用。

公开(公告)号：EP1797501A1

公开(公告)日：2007-06-20

申请号：EP05786579.2

申请日：2005-09-19

申请人： SAP AG

发明人： SCHMIDT, Oliver

IPC分类号： G06F9/46

CPC分类号： G06F9/544 ,  G06F9/461 ,  G06F9/52

摘要： Systems and techniques for transferring the flow of control between agents. In one general aspect, a computer program product includes instructions operable to cause data processing apparatus to: store data on a first call stack, the first call stack corresponding to and being used by a first agent; suspend the first agent's use of the first call stack; enable a second agent to access the data by using the first call stack; and resume the first agent's use of the first call stack after the second agent is no longer using the first call stack. According to another aspect, a computer program product includes a first set of instructions that is operable to store and access data on a shared call stack; and a second set of instructions that is operable to alternate execution of the first set of instructions between a first agent and a second, distinct agent.

公开(公告)号：EP1794673A2

公开(公告)日：2007-06-13

申请号：EP05786903.4

申请日：2005-09-23

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： BITTERLICH, Jean-Yves

IPC分类号： G06F9/445

CPC分类号： G06F9/461 ,  G06F8/656

摘要： The aim of the invention is to be able to carry out the distribution of software and configuration data in data networks with a plurality of subscribers in a temporally defined manner. To this end, the software or data to be distributed is subdivided into data blocks (A, B, C) and a corresponding list (L) is generated. A first data block (B) and the list (L) are sent from a control centre (O) to a first subscriber (T2). Once a pre-determinable length of time has passed following the reception of the list (L), the subscriber (T2) demands the missing data blocks (C) from the control centre (O). The missing data blocks (C) are then sent from the control centre (O) to the subscriber (T2) such that the subscriber has a complete set of data blocks and can start an installation for example.

公开(公告)号：EP1785863A2

公开(公告)日：2007-05-16

申请号：EP07101869.1

申请日：2001-01-25

申请人： FUJITSU LIMITED

发明人： MIYAKE, Hideo ,  SUGA, Atsuhiro ,  NAKAMURA, Yasuki ,  TSUJI, Masayuki ,  YAMAZAKI, Yasuhiro ,  TAKEBE, Yoshimasa ,  SATO, Taizo ,  TAGO, Shinichiro

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/461 ,  G06F9/5016 ,  G06F2207/5353 ,  Y02D10/22

摘要： A divider, comprising: a carry save adder (2014); and a full adder (2103) connected in series with said carry save adder (2014), wherein the series connection of said carry save adder and said full adder performs an addition computation necessary for division computation.

摘要翻译： 一种分频器，包括：进位保存加法器（2014）; 以及与所述进位存储加法器（2014）串联连接的全加器（2103），其中所述进位存储加法器和所述全加器的串联连接执行分割计算所需的加法运算。

公开(公告)号：EP1785862A2

公开(公告)日：2007-05-16

申请号：EP07101868.3

申请日：2001-01-25

申请人： FUJITSU LIMITED

发明人： MIYAKE, Hideo ,  SUGA, Atsuhiro ,  NAKAMURA, Yasuki ,  TSUJI, Masayuki ,  YAMAZAKI, Yasuhiro ,  TAKEBE, Yoshimasa ,  SATO, Taizo ,  TAGO, Shinichiro

IPC分类号： G06F9/46 ,  G06F9/38

CPC分类号： G06F7/535 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/461 ,  G06F9/5016 ,  G06F2207/5353 ,  Y02D10/22

摘要： A method of pipeline processing that attends to computation by connecting a central processing unit to an additional computation unit, comprising the steps of: storing a computation instruction supplied to the computation unit; executing the stored computation instruction, and checking if completing the execution of the computation instruction requires more than a predetermined time length; shifting the stored computation instruction to a dedicated storage if completing the execution of the computation instruction requires more than the predetermined time length; and executing the computation instruction stored in the dedicated storage until the execution of the computation instruction is completed.

摘要翻译： 一种通过将中央处理单元连接到另外的计算单元而参与计算的流水线处理方法，包括以下步骤：存储提供给计算单元的计算指令; 执行所存储的计算指令，并检查完成计算指令的执行是否需要多于预定时间长度; 如果完成计算指令的执行需要多于预定时间长度，则将存储的计算指令移位到专用存储器; 并且执行存储在专用存储器中的计算指令，直到计算指令的执行完成。