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公开(公告)号：EP2908554A1
公开(公告)日：2015-08-19
申请号：EP15155345.0
申请日：2012-03-08
申请人： NEC Corporation
发明人： Onishi, Yasuharu , Kuroda, Jun , Komoda, Motoyoshi , Kishinami, Yuichiro , Satou, Shigeo , Murata, Yukio , Kawashima, Nobuhiro , Uchikawa, Tatsuya
CPC分类号： H03B28/00 , H04R17/00 , H04R2217/03 , H04R2499/11
摘要： Provided is an oscillator (100) including a piezoelectric body (70) that has a plurality of protrusions (72) on one surface thereof, a plurality of electrodes (80) that are respectively provided on the plurality of protrusions (72) so as to be separated from each other, and a plurality of electrodes (82) that are provided on the other surface opposite to the one surface of the piezoelectric body (70) so that each of the electrodes faces only one electrode (80). Thus, it is possible to prevent variation in acoustic characteristics from occurring. Therefore, the oscillator capable of improving the acoustic characteristics of an electronic device is provided.
摘要翻译： 提供了一种振荡器（100），其包括在其一个表面上具有多个突起（72）的压电体（70），分别设置在多个突起（72）上的多个电极（80），以便 彼此分离，并且设置在与压电体（70）的一个表面相对的另一表面上，使得每个电极仅面对一个电极（80）的多个电极（82）。 因此，可以防止发生声学特性的变化。 因此，提供了能够改善电子设备的声学特性的振荡器。
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公开(公告)号：EP2372902B1
公开(公告)日：2015-04-08
申请号：EP11154102.5
申请日：2011-02-11
发明人： Mu, Fenghao , Sjöland, Henrik
CPC分类号： H03B28/00 , H03F1/3247
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73.发明公开
公开(公告)号：EP2779434A1
公开(公告)日：2014-09-17
申请号：EP14157476.4
申请日：2014-03-03
申请人： Analog Devices, Inc.
发明人： Schell, Robert
摘要： Apparatus and methods for quadrature clock signal generation are provided. In certain implementations, an apparatus includes an invertible sine shaping filter configured to receive an in-phase clock signal, a quadrature-phase clock signal, and an inversion control signal. The invertible sine-shaping filter is further configured to filter the in-phase and quadrature-phase clock signals to generate sinusoidal in-phase and quadrature-phase clock signals. The invertible sine-shaping filter is further configured to selectively invert one or both of the in-phase and quadrature-phase clock signals based on an inversion control signal. The apparatus further includes a phase interpolator configured to generate an interpolated clock signal based on a weighted sum of the selectively inverted sinusoidal in-phase clock signal and the quadrature-phase sinusoidal clock signal. The in-phase clock signal and the quadrature-phase clock signal have a quadrature-phase relationship.
摘要翻译： 被提供的装置和用于正交时钟信号产生方法。 在某些实现中，给装置包括：配置成接收在相时钟信号，正交相位的时钟信号，并反转控制信号可逆正弦整形滤波器。 可逆正弦整形滤波器还被配置来过滤同相和正交相位时钟信号以产生同相和正交相位的时钟信号的正弦。 可逆正弦整形滤波器还被配置为选择地反转的一个或两个在同相和正交相的时钟信号基于控制信号的反转。 该装置包括：一个相位内插器进一步被配置以基于所述正弦的加权和有选择地反相的同相时钟信号和正交相正弦时钟信号插值时钟信号，以生成。 同相时钟信号和正交相位时钟信号具有正交相位关系。
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公开(公告)号：EP2737333A1
公开(公告)日：2014-06-04
申请号：EP12740178.4
申请日：2012-07-27
IPC分类号： G01S7/282 , G01S13/02 , H03B28/00 , G01S13/28 , G01S7/03 , H04L27/00 , H03K5/1534 , G01S7/288
CPC分类号： H04B1/707 , G01S7/032 , G01S7/282 , G01S13/0209 , G01S13/284 , G01S2007/2886 , H03B28/00 , H03D2200/0019 , H03K5/1534 , H04B1/7172 , H04B1/7174 , H04L27/0004
摘要： The method for operating a UWB device having at least one transmitting antenna and/or at least one receiving antenna comprises the following steps: - triggering the transmitting antenna (12) or the receiving antenna (12') with a triggering pulse signal (13, 13') having a sequence of substantially sinusoidal pulses of alternating polarity and differing amplitudes and particularly having the waveform of a fifth-order Gaussian pulse signal, - wherein the transmitting antenna (12) can be alternately supplied with current pulses of differing polarity and differing magnitude by switching on and off first electronic switch units (16) that are coupled to the transmitting antenna (12) and have resistances associated with the amplitudes of the pulses to be generated, - wherein each first switch unit (16) has a specifiable, particularly equal, number of first switching transistors(18,19), each having substantially identical on-state resistance values (R), - wherein the resistance of a first switch unit is adjusted either by using only one of the first switching transistors (18,19) or by using a plurality of first switching transistors (18,19) connected in parallel, and - wherein the first switch units (16) are triggered sequentially according to a first specifiable temporal schema and each for a triggering time interval of a predetermined length.
摘要翻译： 用于操作具有至少一个发射天线和/或至少一个接收天线的UWB设备的方法包括以下步骤：利用控制脉冲信号（13,13）来控制发射天线（12）或接收天线（12'） '）具有交替极性和不同幅度的基本正弦波脉冲序列，并且特别地具有五阶高斯脉冲信号的波形，其中发射天线（12）可以交替地被提供具有不同极性和不同幅度的电流脉冲， 打开和关闭耦合到所述发射天线（12）并且具有与要产生的脉冲的幅度相关联的电阻的第一电子开关单元（16），其中每个第一开关单元（16）具有可指定的，特别相等的， 第一开关晶体管（18,19）的数量，每个具有基本相同的导通状态电阻值（R），其中第一开关单元 通过仅使用第一开关晶体管（18,19）中的一个或通过并联连接的多个第一开关晶体管（18,19）进行调整，并且其中第一开关单元（16）根据 可指定的时间模式，并且每个用于预定长度的控制时间间隔。
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公开(公告)号：EP1604454B1
公开(公告)日：2011-06-01
申请号：EP04719476.6
申请日：2004-03-11
申请人： Nokia Corporation
发明人： JARSKE, Petri
IPC分类号： H03B28/00
CPC分类号： H03B28/00
摘要： Methods, devices and a software product for generating a sinusoidal signal. If the desired frequency is higher than the upper limit, a coefficient is determined as a function of a multiple of the sampling rate. A sample of the first output sample sequence is determined as a linear combination of the coefficient and previous output samples. The first output sample sequence is decimated so as to generate the desired sinusoidal signal. If the desired frequency is lower than the lower limit, the coefficient is determined as a function of the multiple of the sampling rate. The sample of the first output sample sequence is determined as a linear combination of the coefficient and previous output samples. The first output sample sequence is multiplied so as to generate a second output sample sequence, which is decimated so as to generate the desired sinusoidal signal.
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公开(公告)号：EP1639702B1
公开(公告)日：2008-11-19
申请号：EP03735328.1
申请日：2003-06-27
申请人： The TC Group A/S
CPC分类号： H03F1/08 , H03F3/217 , H03F2200/78
摘要： The invention relates to a self-oscillating circuit comprising comparator means (CM) comprising at least one input means (IM) and at least one output means (OM), at least one of said at least one output means (OM) is coupled to at least one of said at least one input means (IM) via at least one filtering means (FM), said at least one filtering means (FM) at least partly comprising demodulation means (DM), wherein said filtering means (FM) is of at least fifth order.
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77.发明公开Waveform generation method, waveform generation program, waveform generation circuit and radar apparatus 有权Wellenformerzeugungsverfahren，Wellenformerzeugungsprogramm，Wellenformerzeugungsschaltung und Radarvorrichtung
公开(公告)号：EP1928093A1
公开(公告)日：2008-06-04
申请号：EP07024543.6
申请日：2003-08-25
发明人： Inatsune, Shigeho
CPC分类号： G06F1/0321 , G01S7/4008 , H03M1/1038 , H03M1/66
摘要： A conventional waveform generation circuit was required to increase a number of bits or a sampling rate for a D/A converter to enhance a precision of waveform shaping, and had a problem that a cost was increased. Therefore, as a method for enhancing the precision of waveform shaping, a quantization error of an output waveform is made smaller by controlling an output time interval of an output value from a D/A converter so as to make a difference in an output voltage between target waveform and output waveform smaller. As a result, even if the D/A converter has a small number of bits, the waveform can be generated at high precision. Also, this waveform generation method may be applied to modulation control of a radar apparatus, 6s a result, constituting a small and inexpensive modulation circuit for an oscillator.
摘要翻译： 需要传统的波形生成电路来增加D / A转换器的位数或采样率，以提高波形整形的精度，并且存在成本增加的问题。 因此，作为提高波形整形精度的方法，通过控制来自D / A转换器的输出值的输出时间间隔，使输出波形的量化误差变小，从而使输出波形的输出电压 目标波形和输出波形较小。 结果，即使D / A转换器具有少量的位，也可以高精度地生成波形。 此外，该波形生成方法也可以应用于雷达装置的调制控制，其结果是构成振荡器的小而廉价的调制电路。
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公开(公告)号：EP1897215A1
公开(公告)日：2008-03-12
申请号：EP06765825.2
申请日：2006-06-22
申请人： NXP B.V.
发明人： TOURRET, Jean-Robert
CPC分类号： H03B28/00
摘要： A pseudo-sine signal generation device (D) comprises i) a differential tunable integration means (SI) arranged to generate differential triangular signals (TS) with a chosen constant output amplitude from input differential square signals (SS), and ii) a differential processing means (PM) arranged to apply a chosen transfer function to the differential triangular signals (TS) in order to reject at least a third harmonic thereof when the amplitude of the differential triangular signals (TS) is equal to the chosen constant amplitude and then to output pseudo-sine signals (OS) with a quasi-constant amplitude.
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公开(公告)号：EP1604454A1
公开(公告)日：2005-12-14
申请号：EP04719476.6
申请日：2004-03-11
申请人： Nokia Corporation
发明人： JARSKE, Petri
IPC分类号： H03B28/00
CPC分类号： H03B28/00
摘要： Methods, devices and a software product for generating a sinusoidal signal. If the desired frequency is higher than the upper limit, a coefficient is determined as a function of a multiple of the sampling rate. A sample of the first output sample sequence is determined as a linear combination of the coefficient and previous output samples. The first output sample sequence is decimated so as to generate the desired sinusoidal signal. If the desired frequency is lower than the lower limit, the coefficient is determined as a function of the multiple of the sampling rate. The sample of the first output sample sequence is determined as a linear combination of the coefficient and previous output samples. The first output sample sequence is multiplied so as to generate a second output sample sequence, which is decimated so as to generate the desired sinusoidal signal.
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公开(公告)号：EP1037379A3
公开(公告)日：2005-08-17
申请号：EP00301410.7
申请日：2000-02-23
申请人： ANALOG DEVICES, INC.
发明人： Ribner, David B. , Kidambi, Sunder
CPC分类号： H03B28/00 , G06F1/0328 , G06F1/0342
摘要： A direct-digital synthesizer (20) for generating a waveform includes a digital accumulator (22) fed by a phase increment word (X) and a series of clock pulses (CK) for successively adding the phase increment word (X) to produce a series of N bit phase words (Y). A table or trigonometric engine (24) produces sine and cosine digital signals related to the M most significant bits of the phase word (Y) produced by the accumulator (22). A feedback loop (30) is fed by truncation error words (T(Z)) comprising at least a portion of N-M least significant bits (32) of the N bit phase words (Y) producing truncation error compensation words. The feedback loop (30) includes a digital filter (34) and provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC. The truncation error response has a transfer function comprising the term (1-az -1 ) where: z is the discrete time frequency variable and a is a unity or non-unity weighting factor. One such filter (34, Fig. 4A) includes an adder (Ao) fed by the truncation error words and a storage device (D) fed by the clock pulses (CK) and by the truncation error words for producing at an output thereof the truncation error words delayed by each one of the clock pulses (CK) fed thereto. The adder (Ao) is fed by the output of the storage device (D) to produce an algebraic sum of the truncation error words fed to the adder (Ao) and the delayed truncation error words.
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