公开(公告)号：EP2904702A1

公开(公告)日：2015-08-12

申请号：EP13762153.8

申请日：2013-09-16

Applicant: Telefonaktiebolaget LM Ericsson (Publ)

Inventor： SUNDSTRÖM, Lars ,  EK, Staffan

IPC: H03D7/16 ,  G06F1/03 ,  H04L27/38

CPC classification number: G06F1/0342 ,  H03D7/165

Abstract: The teachings presented herein allow the same sequence of local oscillator waveform sample values to be used for driving two harmonic rejection mixers for which quadrature operation is desired, irrespective of whether the oversampling rate of the sequence is divisible by four or only divisible by two. This ability is obtained by controlling whether the quadrature mixer clocks coincidentally with the ίη-phase mixer, or clocks a half clock cycle out of phase relative to the in-phase mixer. Several advantages attend the contemplated circuit arrangement and method of operation. Example advantages include the improved matching that comes from operating both mixers with the identical waveform sample values, and the improved flexibility in optimizing the harmonic rejection and/or interference- related operation of the mixers over a broader range of frequencies of interest, which flows from having a larger set of usable OSRs.

公开(公告)号：EP1037379A2

公开(公告)日：2000-09-20

申请号：EP00301410.7

申请日：2000-02-23

Applicant: ANALOG DEVICES, INCORPORATED

Inventor： Ribner, David B. ,  Kidambi, Sunder

IPC: H03B28/00

CPC classification number: H03B28/00 ,  G06F1/0328 ,  G06F1/0342

Abstract: A direct-digital synthesizer (20) for generating a waveform includes a digital accumulator (22) fed by a phase increment word (X) and a series of clock pulses (CK) for successively adding the phase increment word (X) to produce a series of N bit phase words (Y). A table or trigonometric engine (24) produces sine and cosine digital signals related to the M most significant bits of the phase word (Y) produced by the accumulator (22). A feedback loop (30) is fed by truncation error words (T(Z)) comprising at least a portion of N-M least significant bits (32) of the N bit phase words (Y) producing truncation error compensation words. The feedback loop (30) includes a digital filter (34) and provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC. The truncation error response has a transfer function comprising the term (1-az -1 ) where: z is the discrete time frequency variable and a is a unity or non-unity weighting factor. One such filter (34, Fig. 4A) includes an adder (Ao) fed by the truncation error words and a storage device (D) fed by the clock pulses (CK) and by the truncation error words for producing at an output thereof the truncation error words delayed by each one of the clock pulses (CK) fed thereto. The adder (Ao) is fed by the output of the storage device (D) to produce an algebraic sum of the truncation error words fed to the adder (Ao) and the delayed truncation error words.

Abstract translation: 用于产生波形的直接数字合成器（20）包括由相位增量字（X）和一系列时钟脉冲（CK）馈送的数字累加器（22），用于连续添加相位增量字（X）以产生 系列N位相位字（Y）。 表或三角引擎（24）产生与由累加器（22）产生的相位字（Y）的M个最高有效位相关的正弦和余弦数字信号。 产生截断误差补偿字的N位相位字（Y）的N-M个最低有效位（32）的至少一部分的截断误差字（T（Z））馈送反馈回路30。 反馈回路（30）包括数字滤波器（34），并且在DC的传递函数中具有至少一个零的截断误差提供低通截断误差响应。 截断误差响应具有包括项（1-az <-1>）的传递函数，其中：z是离散时间频率变量，a是单位或非单位加权因子。 一个这样的滤波器（图4A中的34）包括由截断误差字馈送的加法器（Ao）和由时钟脉冲（CK）馈送的存储装置（D）和用于在其输出端产生的截断误差字， 截断错误字被馈送到其中的每个时钟脉冲（CK）延迟。 加法器（Ao）由存储装置（D）的输出馈送，以产生馈送到加法器（Ao）的截断误差字和延迟的截断误差字的代数和。

公开(公告)号：EP0440187A2

公开(公告)日：1991-08-07

申请号：EP91101199.7

申请日：1991-01-30

Applicant: NEC CORPORATION

Inventor： Ichihara, Masaki, c/o NEC Corporation

IPC: H04L27/20 ,  H04L27/12

CPC classification number: G06F1/0353 ,  G06F1/0342 ,  H04L25/03834

Abstract: In order to effectively reduce a memory size of each of two memories (60,62) provided in an arrangement for converting a binary input data into the corresponding in-phase and quadrature signals, a memory output controller(64) and a sequential logic (66) are provided. The memory output controller (64) includes two polarity control circuits (76,78) and two input data selectors (80,82). The two polarity control circuits (76, 78) are respectively coupled to the two memories (60,62), while the two input data selectors (80,82) are preceded by and coupled to both of the two polarity control circuits (76,78). Each of the two polarity control circuits (76,78) reverses the polarity of the output of the associated memory according to the output of the sequential logic. On the other hand, each of the two input data selectors (80,82) is arranged to selectively acquire the outputs of the two polarity control circuits (76,78) depending on the output of the sequential logic (66).

Abstract translation: 为了有效地减少用于将二进制输入数据转换为对应的同相和正交信号的装置中提供的两个存储器（60,62）中的每一个的存储器大小，存储器输出控制器（64）和顺序逻辑（ 66）。 存储器输出控制器（64）包括两个极性控制电路（76,78）和两个输入数据选择器（80,82）。 两个极性控制电路（76,78）分别耦合到两个存储器（60,62），而两个输入数据选择器（80,82）在两个极性控制电路（76,88）之前并耦合到两个极性控制电路 78）。 两个极性控制电路（76,78）中的每一个根据顺序逻辑的输出反转相关存储器的输出的极性。 另一方面，两个输入数据选择器（80,82）中的每一个被布置成根据顺序逻辑（66）的输出选择性地获取两个极性控制电路（76,78）的输出。

公开(公告)号：EP0259514A1

公开(公告)日：1988-03-16

申请号：EP86112597.9

申请日：1986-09-11

Applicant: Deutsche ITT Industries GmbH

Inventor： Mehrgardt, Sönke, Dr. ,  Schemmann, Heinrich, Dipl.-Ing.

IPC: G06F1/02 ,  H04N9/64

CPC classification number: G06F1/0342 ,  G06F1/0353 ,  H04N9/643

Abstract: Diese Schaltung liefert zu ein und demselben digitalen Argument (p) aus einem beliebigen Quadranten der Sinus- und Cosinusfunktion gleichzeitig die entsprechenden Sinus- und Cosinusfunktionswerte (s..,c..). Dazu dient im wesentlichen der Festwertspeicher (rm), in dessen beiden Speicherhälften (h1, h2) die vorzeichenstellenlosen Funktionswerte des ersten Halbquadranten bzw. des zweiten Halbquadranten der Cosinusfunktion einmal in Richtung zunehmender und einmal in Richtung abnehmender Argumente (p) abgelegt sind. Dabei ist die Stellenzahl (m) des Arguments (p) um drei größer als die Stellenzahl (n) der Funktionswerte inkl. von deren Vorzeichenstelle. Durch geschickte Invertierung der Adressen und der ausgelesenen Funktionswerte mittels der Vielfachinverter (i1, i2, i3) in Verbindung mit den Vielfachumschaltern (u1..u5) lassen sich die Sinus- und Cosinusfunktionswerte sowohl im Einer- als auch im Zweierkomplementcode für alle vier Quadranten erzeugen. Wird das Argument (p) mittels des Akkumulators (ak) gebildet, an dessen Eingang das frequenzbestimmende Digitalwort (f) liegt, so ist die Digitalschaltung ein digitaler Sinus/Cosinusoszillator.

Abstract translation: 该电路提供在一个和从正弦和余弦函数的任何象限在同一时间同一数字参数（p）的对应的正弦和Cosinusfunktionswerte（S ..，C ...）。 基本上用于在两个存储器半部只读存储器（RM）（H1，H2）的第一半象限和余弦函数的第二半象限中的有符号位随机函数值存储一次在增加的方向上，并且一旦在降低参数（p）的方向。 在这种情况下，参数（p）的位数（M）的数量为约三比的函数值含的数字（n）的数多。符号位数。 由熟练的由所述多个逆变器的装置（I1，I2，I3）可以与所述多个开关（u1..u5）结合以产生用于所有四个象限的正弦和Cosinusfunktionswerte二者的那些也如在二的补码反相的地址和读出的函数值 ， 形成，由累加器（AK）的装置参数（P），在其输入端的频率确定数字字（f）中，因此数字电路是一种数字正弦/ Cosinusoszillator。

公开(公告)号：EP3355816A1

公开(公告)日：2018-08-08

申请号：EP16778967.6

申请日：2016-09-26

Applicant: Ethicon LLC

Inventor： WIENER, Eitan T. ,  YATES, David C.

IPC: A61B18/12 ,  A61B18/14 ,  A61B17/29 ,  A61B17/32 ,  A61B18/00 ,  G06F1/03 ,  H03M1/66

CPC classification number: A61B18/1206 ,  A61B17/320068 ,  A61B17/320092 ,  A61B18/1445 ,  A61B2018/00607 ,  A61B2018/00678 ,  A61B2018/00684 ,  A61B2018/00994 ,  G06F1/0321 ,  G06F1/0342 ,  H03M1/66

Abstract: A method of generating electrical signal waveforms. A generator includes a digital processing circuit, a memory circuit in communication with the digital processing circuit defining a lookup table, a digital synthesis circuit in communication with the digital processing circuit and the memory circuit, and a digital-to-analog converter (DAC) circuit. The method includes generating a first and second digital electrical signal waveforms, combining the first and second waveforms to form a combined waveform, modifying the combined waveform to form a modified waveform The peak amplitude of the modified waveform does not exceed a predetermined amplitude value. The method includes generating a second waveform that is a function of the first waveform. The method includes modifying a frequency of the first waveform to form a frequency modified first waveform and combining the frequency modified first and second waveforms to form a combined waveform.

公开(公告)号：EP0829950B1

公开(公告)日：1999-08-25

申请号：EP96114782.4

申请日：1996-09-16

Applicant: Schöller, Kurt ,  Cappel, Harald

Inventor： Schöller, Kurt ,  Fiedler, Meinrad, Dipl.-Ing. ,  Böttcher, Georg, Dipl.-Ing. ,  Wasenmüller, Uwe, Dipl.-Ing.

IPC: H02M7/48 ,  G06F1/03

CPC classification number: H02M7/53873 ,  G06F1/0342 ,  G06J1/00

公开(公告)号：EP0829950A1

公开(公告)日：1998-03-18

申请号：EP96114782.4

申请日：1996-09-16

Applicant: Schöller, Kurt ,  Cappel, Harald

Inventor： Schöller, Kurt ,  Fiedler, Meinrad, Dipl.-Ing. ,  Böttcher, Georg, Dipl.-Ing. ,  Wasenmüller, Uwe, Dipl.-Ing.

IPC: H02M7/48 ,  G06F1/03

CPC classification number: H02M7/53873 ,  G06F1/0342 ,  G06J1/00

Abstract: Die Erfindung betrifft einen digitalen, frequenz- und amplitudenvariablen Drehstromgenerator (1) mit mindestens einem Sinusgenerator (2, 3, 4), der insbesondere als Digital/Analog-Wandler ausgebildet ist, und mindestens einem digital gesteuerten Oszillator (6), von denen die Sinusgeneratoren (2, 3, 4) mit variabler Frequenz angesteuert werden, wobei Amplitudenwerte erzeugt werden, indem Amplitudenzähler (34) synchron zu Zähler (31) für Phasenwerte hoch- oder runtergezählt werden. Ein Ordinatenspeicher (33) enthält die Amplitudenwerte adressierbar, wobei die Adressen der Amplitudenwerte von Zählern (31, 34) angegeben werden. Eine Frequenzsteuerung ist vorgesehen, die zwischen einer einstellbaren Start- und einer Endfrequenz dem digital gesteuerten Oszillator (6) die Variation der Frequenzen vorgibt, und eine Schnittstelle (15), die zur Bestimmung der Frequenzen und Amplituden der Signale der Sinusgeneratoren (2, 3, 4) Werte entgegennimmt oder ausgibt.

Abstract translation: 发电机（1）具有DC到AC转换器形式的至少一个正弦波发生器（2,3,4）。 振荡器（6）根据相位值将振幅信号设置为高或低，来控制发生器。 振幅值存储在可寻址存储器中。 振荡器的频率可以通过控制来设置。 频率和幅度可以通过接口（15）设置或查询。

公开(公告)号：EP0528565B1

公开(公告)日：1996-06-05

申请号：EP92306939.7

申请日：1992-07-30

Applicant: MATRA MARCONI SPACE UK LIMITED

Inventor： Parkes, Stephen Maxwell, c/o British Aerospace

IPC: G06F1/03 ,  H03B23/00

CPC classification number: G06F1/0342 ,  H03B23/00 ,  H03B2200/0092

公开(公告)号：EP0528565A2

公开(公告)日：1993-02-24

申请号：EP92306939.7

申请日：1992-07-30

Applicant: MATRA MARCONI SPACE UK LIMITED

Inventor： Parkes, Stephen Maxwell, c/o British Aerospace

IPC: G06F1/03 ,  H03B23/00

CPC classification number: G06F1/0342 ,  H03B23/00 ,  H03B2200/0092

Abstract: A digital chirp generator system comprises a plurality of digital chirp generator elements each capable of producing a phase sample at a given relatively low bandwidth and being operable in parallel to produce a plurality of phase samples for being interleaved to provide a sequence of samples corresponding to the phase samples of a single chirp signal at a correspondingly higher bandwidth.

Abstract translation: 数字线性调频脉冲发生器系统包括多个数字线性调频脉冲发生器单元，每个线性调频脉冲发生器单元能够以给定的相对低的带宽产生相位样本，并且可以并行操作以产生多个相位样本以进行交织以提供对应于 在相应较高的带宽上的单个啁啾信号的相位样本。

公开(公告)号：EP0191991A2

公开(公告)日：1986-08-27

申请号：EP85309335.9

申请日：1985-12-20

Applicant: GPT LIMITED

Inventor： Cordwell, Brian ,  Hayes, Paul Malcom

IPC: G06F1/02 ,  H03L7/10 ,  G06F1/03

CPC classification number: G06J1/00 ,  G06F1/0342 ,  G06F7/026 ,  H03L7/093 ,  H03L7/10

Abstract: A control circuit comprising a read-only memory (3) has its storage area divided into two areas each containing the same number of addressable words. By arranging that input of a single address signal (An+1) causes a change from addressing a particular word in one area to addressing a corresponding word in the other area, and by programming a fixed difference in value between corresponding words in the two areas causes a step function in the output. Using a digital to analogue converter (1) on the output of the circuit permits a step change in a voltage output (1) to be provided to (eg) a voltage controlled oscillator (4). A control circuit using a read-only memory as a voltage comparator is also disclosed.