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公开(公告)号：EP2624459B1
公开(公告)日：2018-09-26
申请号：EP10857774.3
申请日：2010-09-28
Applicant: Mitsubishi Electric Corporation
Inventor： ONISHI, Atsuko , KUBOTA, Yoshiyuki
CPC classification number: H03M1/66 , G06F1/0321 , G06F13/4059
Abstract: A D/A converter according to the present invention includes a wave-form data-array memory means for memorizing a wave-form data array configured of a plurality of digital values, a wave-form output-format data memory means for memorizing wave-form output-format data designating a wave-form output period, a digital value output means for sequentially reading out the digital values for each wave-form output period from the wave-form data-array memory means and outputting the values, and a D/A conversion means for converting the digital values outputted from the digital value output means into analog-data values.
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2.发明公开
公开(公告)号：EP3355819A1
公开(公告)日：2018-08-08
申请号：EP16787583.0
申请日：2016-09-26
Applicant: Ethicon LLC
Inventor： WIENER, Eitan T. , YATES, David C.
CPC classification number: A61B18/1206 , A61B17/320068 , A61B17/320092 , A61B18/1445 , A61B2018/00607 , A61B2018/00678 , A61B2018/00684 , A61B2018/00994 , G06F1/0321 , G06F1/0342 , H03M1/66
Abstract: A method of generating electrical signal waveforms. A generator includes a digital processing circuit, a memory circuit in communication with the digital processing circuit defining a lookup table, a digital synthesis circuit in communication with the digital processing circuit and the memory circuit, and a digital-to-analog converter (DAC) circuit. The method includes generating a first and second digital electrical signal waveforms, combining the first and second waveforms to form a combined waveform, modifying the combined waveform to form a modified waveform The peak amplitude of the modified waveform does not exceed a predetermined amplitude value. The method includes generating a second waveform that is a function of the first waveform. The method includes modifying a frequency of the first waveform to form a frequency modified first waveform and combining the frequency modified first and second waveforms to form a combined waveform.
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3.发明公开DEVICE AND METHOD FOR GENERATING SINE WAVE 审中-公开VORRICHTUNG UND VERFAHREN ZUR ERZEUGUNG EINER SINUSWELLE
公开(公告)号：EP3082255A4
公开(公告)日：2017-09-20
申请号：EP14882585
申请日：2014-08-14
Applicant: SHENZHEN HUIDING TECHNOLOGY CO
Inventor： WANG GUANGYAO
CPC classification number: G06F1/0321 , G06F1/022 , G06F1/03 , G06F1/0328 , G06F1/035 , H03K3/012
Abstract: A sine wave generating apparatus comprises: a phase accumulating module, configured to acquire configuration information of a sine wave, and generate address information according to the configuration information, the address information of the sine wave comprising integer address information and decimal address information; a value searching module, configured to search for first data information and second data information of the sine wave according to the integer address information; an interpolation module, configured to conduct interpolation between the first data information and the second data information according to the bit width of the decimal address information, and acquire interpolation original data information of the sine wave according to the decimal address information; a random truncating module, configured to conduct truncation processing on the interpolation original data according to the bit width of the decimal address information and a pseudorandom sequence output value to acquire final interpolation data information of the sine wave; and a sine wave generating module, configured to generate image information of the sine wave according to the final interpolation data information of the sine wave.
Abstract translation: 一种正弦波产生装置，包括：相位累加模块，用于获取正弦波的配置信息，并根据所述配置信息产生地址信息，所述正弦波的地址信息包括整数地址信息和小数地址信息; 值搜索模块，用于根据所述整数地址信息查找所述正弦波的第一数据信息和第二数据信息; 插值模块，用于根据所述小数地址信息的位宽在所述第一数据信息与所述第二数据信息之间进行插值，并根据所述小数地址信息获取所述正弦波的插值原始数据信息; 随机截断模块，用于根据所述小数地址信息的位宽和伪随机序列输出值对所述插值原始数据进行截断处理，以获取所述正弦波的最终插值数据信息; 正弦波生成模块，用于根据所述正弦波的最终插值数据信息生成所述正弦波的图像信息。
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公开(公告)号：EP3114541A1
公开(公告)日：2017-01-11
申请号：EP15703695.5
申请日：2015-01-28
Applicant: Raytheon Company
Inventor： NUSSBAUM, Howard, S.
Abstract: A processing-efficient chirp generator that allows flexibility in controlling phase, frequency and slope, i.e., rate of change of frequency. In one embodiment, a fine phase propagation block generates phase values in increments of the fine time step, each phase value also offset from other phase values by multiples of a coarse time step. The phase samples are realigned in time after conversion to digital-to-analog converter (DAC) values.
Abstract translation: 一种处理有效的啁啾发生器，其允许控制相位，频率和斜率的灵活性，即频率变化率。 在一个实施例中，精细相位传播块以精细时间步长的增量生成相位值，每个相位值也从粗略时间步长的倍数与其它相位值偏移。 在转换为数模转换器（DAC）值后，相位采样在时间上重新对准。
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公开(公告)号：EP3076552A1
公开(公告)日：2016-10-05
申请号：EP15161762.8
申请日：2015-03-30
Applicant: NXP B.V.
Inventor： van de Beek, Remco , Verlinden, Jos , Al-Kadi, Ghiath
CPC classification number: H04L7/033 , G06F1/0321 , H03L7/0992 , H03L7/23 , H04B5/0031 , H04L61/1552
Abstract: A digital synchronizer is disclosed, comprising:
a phase locked loop (100) configured to produce an output signal (clkFc) having the same frequency as an input signal (Frx) by selecting a divider ratio (/P) of a frequency divider (130) with a control signal (Pctrl), the frequency divider (130) configured to divide the frequency of a high frequency signal (clkHF) by the divider ratio (/P) to provide the output signal (clkFc);
a carrier generator (300) comprising a look-up table (320), the carrier generator (300) configured to generate an oversampled carrier signal using the look-up-table (320) by using the control signal (Pctrl) to produce a carrier signal with a period corresponding with a contemporaneous period of the output signal (clkFc).Abstract translation: 公开了一种数字同步器，包括：锁相环（100），被配置为通过选择分频器（130）的分频比（/ P）来产生与输入信号（Frx）具有相同频率的输出信号（clkFc） ），分频器（130）被配置为将高频信号（clkHF）的频率除以分频比（/ P）以提供输出信号（clkFc）; 包括查找表（320）的载波发生器（300），所述载波发生器（300）被配置为使用所述查找表（320）通过使用所述控制信号（Pctr1）产生过采样载波信号，以产生 载波信号具有对应于输出信号（clkFc）的同期期间的周期。
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Patent Agency Ranking
公开(公告)号：EP2746891B1
公开(公告)日：2015-06-03
申请号：EP12198406.6
申请日：2012-12-20
Applicant: IMEC
Inventor： Kim, Sunyoung , Yazicioglu, Refet Firat
CPC classification number: H02J3/00 , G06F1/022 , G06F1/0321 , Y10T307/724
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公开(公告)号：EP1124177B1
公开(公告)日：2012-10-10
申请号：EP00308003.3
申请日：2000-09-14
Applicant: Fujitsu Semiconductor Limited
CPC classification number: G06F1/0321 , G05B2219/21137
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公开(公告)号：EP1124177A3
公开(公告)日：2004-02-25
申请号：EP00308003.3
申请日：2000-09-14
Applicant: FUJITSU LIMITED
CPC classification number: G06F1/0321 , G05B2219/21137
Abstract: A data I/O system includes first and second function blocks connected to a system bus, which allows the function blocks to communicate with a processor. Each function block includes a D/A converter (22) for outputting an analog signal and a waveform generator (21) that provides a digital signal to the D/A converter. The waveform generator includes a memory control circuit (23) and an address generation circuit (24). The memory control circuit has an address register (32) and a data register (33), both of which are connected to the system bus (16), and a memory (31) connected to the address register and the data register. The address generation circuit (24) is connected to the address register and includes a control register (34), an up-down counter (35), and a comparator (36). The address generation circuit repetitively provides a circulating address signal to the address register. The function blocks relieve the processor of some of its processing load, but do not require additional I/O port addresses of the system.
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公开(公告)号：EP1186101A1
公开(公告)日：2002-03-13
申请号：EP00937865.4
申请日：2000-05-26
Applicant: Peco II, Inc.
Inventor： ROLLER, John , KARNES, Jon, Drew
CPC classification number: H02M7/493 , G06F1/0321 , G06F1/0342
Abstract: A digital voltage controlled oscillator is disclosed. The digital voltage controlled oscillator includes an input for receiving input signals representative of a desired frequency. It also includes a pulse generator and a logic circuit. The logic circuit develops an oscillating signal having a predefined waveform and the desired frequency by controlling the energy contained in the pulses output by the pulse generator. The disclosed digital voltage controlled oscillator also includes a capacitor which is charged by the pulses to a voltage that generally varies in accordance with the predefined waveform and the desired frequency.
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公开(公告)号：EP0848317A3
公开(公告)日：1999-11-10
申请号：EP97401711.3
申请日：1997-07-16
Applicant: FUJITSU LIMITED
Inventor： Komura, Tatsuki, c/o Fujitsu Limited
IPC: G06F1/03
CPC classification number: H04Q1/44 , G06F1/0321
Abstract: The signal generating device includes a first part (150) which generates a given signal when an operation control signal applied thereto becomes active, and a second part (200) which causes the first part to continue to generate the given signal until the given signal becomes equal to a given level after the operation control signal becomes inactive.
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