METHOD FOR PROCESSING INTERRUPT AND INTERRUPT PROCESSING DEVICE

    公开(公告)号:EP4439292A1

    公开(公告)日:2024-10-02

    申请号:EP24164809.6

    申请日:2024-03-20

    IPC分类号: G06F9/48 G06F9/32 G06F9/30

    摘要: The present disclosure provides methods and apparatuses for interrupt processing. An interrupt processing method includes executing a first interrupt by using a common register, receiving a second interrupt and a second priority of the second interrupt during execution of the first interrupt, comparing a first priority of the first interrupt with the second priority of the second interrupt, generating a first register index corresponding to the second priority of the second interrupt by using a look-up table based on the second priority of the second interrupt being greater than the first priority, and, based on the first register index being a dedicated index, maintaining a context of the first interrupt stored in the common register, assigning a dedicated register for execution of the second interrupt, and executing an interrupt program corresponding to the second interrupt by using the assigned dedicated register. The interrupt program is saved in a memory.

    SEMICONDUCTOR DEVICE FOR SHARED RESOURCE MANAGEMENT

    公开(公告)号:EP4439227A1

    公开(公告)日:2024-10-02

    申请号:EP24164819.5

    申请日:2024-03-20

    摘要: A semiconductor system includes a shared resource management circuit configured to provide a shared resource having a level adjusted according to a setting level, a plurality of intellectual property (IP) blocks each including at least one core configured to execute an instruction and configured to generate separate, respective control signals of a plurality of control signals, plurality of control signals including separate, respective setting levels of a plurality of setting levels, and a logic circuit including a plurality of slots configured to respectively store the plurality of setting levels respectively included in the plurality of control signals respectively received from the plurality of IP blocks, the logic circuit being configured to select a target setting level from among the plurality of setting levels and transmit, to the shared resource management circuit, a target control signal including the target setting level.

    CEILING-TYPE AIR CONDITIONER
    85.
    发明公开

    公开(公告)号:EP4438962A1

    公开(公告)日:2024-10-02

    申请号:EP22924359.7

    申请日:2022-11-29

    IPC分类号: F24F1/26 F24F1/56 F25B41/20

    CPC分类号: F24F1/26 F24F1/56 F25B41/20

    摘要: Various embodiments disclosed herein relate to a bracket structure for fastening pipes in an outdoor unit of an air conditioner. To this end, the outdoor unit of the air conditioner may include: a bracket configured by fastening a right-side part of an upper plate and a left-side part of a lower plate so that the surfaces thereof partially overlap, wherein one or a plurality of first service valves are mounted on the right-side part of the upper plate and one or a plurality of second service valves are mounted on the left-side part of the lower plate; and a housing configured so that the bracket is fastened to the lower end of one surface.