摘要:
A spectrum analyzer provided with a sync signal input terminal (27A) and a sweep control signal generator (32) inserted between the terminal (27A) and a ramp/address generator (23). When the frequency of a burst wave input signal Sx is analyzed, an external sync signal SY in synchronism with the burst wave is applied to the terminal (27A). As a result the generator (32) generates a sweep control signal SC which rises a predetermined time after the sync signal SY and has a predetermined width. This sweep control signal is applied to the generator (32) so as to sweep a ramp voltage for controlling a local oscillator (16) inside each burst and an address AD for reading a signal take-in memory (19). The sweep operation is stopped during other periods.
摘要:
Periods P k between the one edges of input pulses (A,B) are measured one after another by a successive period measuring circuit (14), and at the same time, the time interval between the one edge to the other of each input pulse, that is, a pulse width W k , is measured by a time interval measuring circuit (15). The measured periods are sequentially accumulated and each accumulated value is made to correspond to each pulse, as the time at which the measurement of its pulse width was started. In an interpolation part (26), pulse widths, which are assumed to be obtained at regular time intervals, are computed, by an interpolation method, from the sequence of measured pulse widths and the their measurement starting times. In a Fourier transform part (27), the pulse width data obtained by the interpolation is subjected to a Fourier transform to obtain the frequency components of a pulse width jitter.
摘要:
A single-crystal substrate (12) is prepared which has the (100) crystal plane with a step line (13) formed therein by cleaving an MgO single crystal. By evaporating metal onto the cleavage plane, with a mask wire (18) of platinum disposed at a distance from the cleavage plane and extended in a direction across the step line, a pair of metal thin film electrodes (14,15) separated by a gap (24) are epitaxially grown. By this, a step line (17) corresponding to the cleavage-plane step line is formed in the surface of each of the metal thin film electrodes. Metal is further evaporated onto the metal thin film electrodes at a low rate, by which nano-size thin wires (22) extending along the step lines are grown so that they approach each other and are finally connected to each other.
摘要:
A plurality of delay stages (21) are connected in cascade, each delay stage having a construction in which either one of a path of a delay element (17) utilizing the propagation delay of a gate array and a path (18) not passing through the delay element is selected by a path selector (19). Each bit of control data is used to control the path selector of the corresponding delay stages. Composite delays are measured for all combinations of such paths, control data (D C ) which provides a measured composite delay closest to an intended delay corresponding to each set data (D L ) is determined and is prestored in a main conversion table (22). A prediction is made, through calculation, as to a delay for each control data when ambient temperature rises △T°C from a temperature T O at which the main conversion table was produced, the thus predicted delay is used to determine control data which provides a predicted delay closest to an intended delay for each set data, and the relationship between the control data and the set data is prestored in a corrected conversion table (31, 32). Ambient temperature is detected by temperature detection/control circuit (36). When the difference △t between the detected temperature and the temperature t O is △t
摘要翻译:多个延迟级(21)级联连接,每个延迟级具有利用门阵列的传播延迟的延迟元件(17)的路径和不通过的路径(18)的结构 延迟元件由路径选择器(19)选择。 控制数据的每一位用于控制相应延迟级的路径选择器。 对这种路径的所有组合测量复合延迟,确定提供最接近对应于每个集合数据(DL)的预期延迟的测量复合延迟的控制数据(DC),并将其预存储在主转换表(22)中。 通过计算,当环境温度从产生主转换表的温度T0升高到INCREMENT T°C时,通过计算来预测每个控制数据的延迟,由此预测的延迟用于确定提供 预测延迟最接近于每个设定数据的预期延迟,并且控制数据与设定数据之间的关系预先存储在校正转换表(31,32)中。 环境温度由温度检测/控制电路(36)检测。 当检测温度和温度t0之间的差值INCREMENT t为INCREMENT t / = INCREMENT T DEGC时,选择校正的转换表的控制数据,并且相应地控制每个延迟级的路径选择器。
摘要:
Frequency division circuits (12₁-12 n )in n stages sequentially 1/2-frequency-divide an input clock signal. Pattern generating circuit (13) generates and issues a plurality of pattern data parallel to each other in synchronism with a frequency-divided clock from the final frequency division stage thereof. Multiplexing circuits (14₁-14 n ) in n stages are given a plurality of pattern data and multiplex input pattern data in each stage for each two data. Output clock signals of the n-th through first stage frequency division circuits are supplied to the first through n-th multiplexing circuits via respective delay circuits (15₁-15 n ) as multiplexing control clock signals. a retiming circuit (27) is inserted in series to the input of at least one of the multiplexing circuits, and a multiplexing control clock signal applied to said one multiplexing circuit from the corresponding frequency division circuit is given to the retiming circuit as a retiming clock signal. A phase switching circuit (28) is inserted in series to the output of the frequency division circuit which applies the multiplexing control clock signal to said one multiplexing circuit. When a node of the input pattern data in the retiming circuit approaches the edge of a retiming clock signal within a predetermined range, an approach detection signal is issued from the approach detection circuit (31). The phase switching circuit shifts the phase of the input clock signal in response to the approach detection signal by a predetermined quantity and issues the phase-shifted clock signal.
摘要:
Pins of an IC under test are classified into pin groups according to the delay time to be set for a test clock for each pin, and a table of pin group data, which has, at a bit position corresponding to each pin, a "1" or "0" which indicates whether the pin belongs to each pin group, is stored in a pin group table memory (24). The bit positions of the logical values "1", indicating that the pins belong to the pin group, in each pin group data read out from the pin group table memory are sequentially encoded by a priority encoder (26) in an ascending (or descending) order and the delay data is provided to a delay data memory (23). The delay time data common to all the pins belonging to the pin group provided from a tester processor (10) is written into sequentially specified addresses, by which the delay time data for all of the pins can be written into the delay data memory from the tester processor in a short time.
摘要:
A liquid crystal device (17) is disposed on an optical path for irradiating a workpiece (24) with a laser beam from a laser (11). The laser beam is applied via the liquid crystal device to the workpiece after the diameter of the laser beam is enlarged by an expander (14). A beam cross-sectional pattern, which defines desired configuration and a desired intensity distribution of the laser beam, is selectively displayed on the liquid crystal device.
摘要:
A reference beam is allowed to be incident into a Michelson interferometer and a reference interference electric signal which changes sinusoidally with the movement of a movable reflector (14) in accordance with interference of the reference beam is obtained. A control circuit (21) applies a direction control signal representing the direction of the movement of the movable reflector (14) to a two-phase signal generator (32B). In response to the indicated direction, this generator generates a two-phase signal either one of the phases of which is advanced by 90°, and applies this two-phase signal as a feedback signal to a servo driving circuit (19). The control circuit (21) applies a movement control signal to the servo driving circuit (19) and controls the movement of the movable reflector (14), so that high precision control becomes possible in accordance with accuracy of the wavelength of the reference beam.